Jong-Hoon Oh

Person

Chapel Hill, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit including multiple memory devices
- Patent number 8,898,400
- Issue date Nov 25, 2014
- Infineon Technologies AG
- Ralf Klein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to reduce power consumption by transferring fu...
- Patent number 8,797,811
- Issue date Aug 5, 2014
- Qimonda AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip package with interconnected stacked chips
- Patent number 8,138,610
- Issue date Mar 20, 2012
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory refresh system and method
- Patent number 7,975,170
- Issue date Jul 5, 2011
- Qimonda AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure of expanding, upgrading, or fixing multi-chip...
- Patent number 7,944,047
- Issue date May 17, 2011
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and circuit for transmitting a memory clock signal
- Patent number 7,886,122
- Issue date Feb 8, 2011
- Qimonda North America Corp.
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for synchronizing memory enabled systems with...
- Patent number 7,882,324
- Issue date Feb 1, 2011
- Qimonda AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction in memory devices
- Patent number 7,861,138
- Issue date Dec 28, 2010
- Qimonda AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory having a bank with sub-banks
- Patent number 7,782,703
- Issue date Aug 24, 2010
- Qimonda North America Corp.
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
System memory device having a dual port
- Patent number 7,725,609
- Issue date May 25, 2010
- Qimonda AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing memory enabled systems using...
- Patent number 7,721,010
- Issue date May 18, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-diagnostic scheme for detecting errors
- Patent number 7,694,196
- Issue date Apr 6, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure to share internally generated voltages between chips in MCP
- Patent number 7,688,665
- Issue date Mar 30, 2010
- Qimonda North America Corp.
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip package with clock frequency adjustment
- Patent number 7,617,067
- Issue date Nov 10, 2009
- Infineon Technologies AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abbreviated burst data transfers for semiconductor memory
- Patent number 7,617,354
- Issue date Nov 10, 2009
- Qimonda North America Corp.
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique to read special mode register
- Patent number 7,610,455
- Issue date Oct 27, 2009
- Infineon Technologies AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory configured on a common substrate
- Patent number 7,539,034
- Issue date May 26, 2009
- Qimonda North America Corp.
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared interface for components in an embedded system
- Patent number 7,451,263
- Issue date Nov 11, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system
- Patent number 7,434,018
- Issue date Oct 7, 2008
- Infineon Technologies North America Corp.
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method of operating memory system
- Patent number 7,426,607
- Issue date Sep 16, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for early write termination in a semiconductor...
- Patent number 7,414,899
- Issue date Aug 19, 2008
- Infineon Technologies North America Corp.
- Jong Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique to suppress bitline leakage current
- Patent number 7,414,896
- Issue date Aug 19, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for communicating command and address signals
- Patent number 7,405,992
- Issue date Jul 29, 2008
- Qimonda North America Corp.
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to suppress leakage current
- Patent number 7,397,708
- Issue date Jul 8, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit configuration for refreshing data in a semicondu...
- Patent number 7,345,940
- Issue date Mar 18, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock circuit for semiconductor memories
- Patent number 7,345,948
- Issue date Mar 18, 2008
- Infineon Technologies AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal voltage generator with temperature control
- Patent number 7,266,031
- Issue date Sep 4, 2007
- Infineon Technologies AG
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access using multiple sets of address/data lines
- Patent number 7,266,667
- Issue date Sep 4, 2007
- Infineon Technologies AG
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy circuits for semiconductor memory
- Patent number 7,224,626
- Issue date May 29, 2007
- Infineon Technologies AG
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin-cell bit line sensing configuration
- Patent number 7,177,216
- Issue date Feb 13, 2007
- Infineon Technologies AG
- Jungwon Suh
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus to Reduce Power Consumption by Transferring Fu...
- Publication number 20100124130
- Publication date May 20, 2010
- QIMONDA NORTH AMERICA CORPORATION
- Jong-Hoon Oh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE
- Publication number 20090200652
- Publication date Aug 13, 2009
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS
- Publication number 20090196116
- Publication date Aug 6, 2009
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS
- Publication number 20090129186
- Publication date May 21, 2009
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...
- Publication number 20090113158
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...
- Publication number 20090113078
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...
- Publication number 20090079055
- Publication date Mar 26, 2009
- JONG HOON OH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
- Publication number 20090080279
- Publication date Mar 26, 2009
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES
- Publication number 20090031077
- Publication date Jan 29, 2009
- Ralf Klein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early Write Method and Apparatus
- Publication number 20090021995
- Publication date Jan 22, 2009
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY REFRESH SYSTEM AND METHOD
- Publication number 20080313494
- Publication date Dec 18, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MODIFYING A BURST LENGTH FOR SEMICONDUCTOR...
- Publication number 20080301391
- Publication date Dec 4, 2008
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Abbreviated Burst Data Transfers for Semiconductor Memory
- Publication number 20080219074
- Publication date Sep 11, 2008
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configured on a common substrate
- Publication number 20080189480
- Publication date Aug 7, 2008
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH MULTIPLE CONFIGURATIONS
- Publication number 20080162857
- Publication date Jul 3, 2008
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING A SHARED BUS
- Publication number 20080147940
- Publication date Jun 19, 2008
- Rom-Shen Kao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION IN MEMORY DEVICES
- Publication number 20080133994
- Publication date Jun 5, 2008
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR COMMUNICATING COMMAND AND ADDRESS SIGNALS
- Publication number 20080106967
- Publication date May 8, 2008
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUIT FOR TRANSMITTING A MEMORY CLOCK SIGNAL
- Publication number 20080052481
- Publication date Feb 28, 2008
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Memory system
- Publication number 20080025128
- Publication date Jan 31, 2008
- Infineon Technologies North America Corp.
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for early write termination in a semiconducuto...
- Publication number 20070253262
- Publication date Nov 1, 2007
- Jong Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Shared interface for components in an embedded system
- Publication number 20070186061
- Publication date Aug 9, 2007
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency circuit for semiconductor memories
- Publication number 20070171735
- Publication date Jul 26, 2007
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Clock circuit for semiconductor memories
- Publication number 20070091710
- Publication date Apr 26, 2007
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Technique to suppress bitline leakage current
- Publication number 20070058447
- Publication date Mar 15, 2007
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Shared interface semiconductor memories
- Publication number 20070033336
- Publication date Feb 8, 2007
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to suppress leakage current
- Publication number 20070030738
- Publication date Feb 8, 2007
- Jong-Hoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-port semiconductor memories
- Publication number 20070033348
- Publication date Feb 8, 2007
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Random access memory having ECC
- Publication number 20060282755
- Publication date Dec 14, 2006
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to read special mode register
- Publication number 20060259711
- Publication date Nov 16, 2006
- Jong-Hoon Oh
- G06 - COMPUTING CALCULATING COUNTING

Jong-Hoon Oh

Person

Patents Grantslast 30 patents

Integrated circuit including multiple memory devices

Method and apparatus to reduce power consumption by transferring fu...

Multi-chip package with interconnected stacked chips

Memory refresh system and method

Method and structure of expanding, upgrading, or fixing multi-chip...

Method and circuit for transmitting a memory clock signal

Method and apparatus for synchronizing memory enabled systems with...

Error correction in memory devices

Semiconductor memory having a bank with sub-banks

System memory device having a dual port

Method and apparatus for implementing memory enabled systems using...

Self-diagnostic scheme for detecting errors

Structure to share internally generated voltages between chips in MCP

Multichip package with clock frequency adjustment

Abbreviated burst data transfers for semiconductor memory

Technique to read special mode register

Memory configured on a common substrate

Shared interface for components in an embedded system

Memory system

Memory system and method of operating memory system

Method and apparatus for early write termination in a semiconductor...

Technique to suppress bitline leakage current

Method and apparatus for communicating command and address signals

Technique to suppress leakage current

Method and circuit configuration for refreshing data in a semicondu...

Clock circuit for semiconductor memories

Internal voltage generator with temperature control

Memory access using multiple sets of address/data lines

Redundancy circuits for semiconductor memory

Twin-cell bit line sensing configuration

Patents Applicationslast 30 patents

Method and Apparatus to Reduce Power Consumption by Transferring Fu...

METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE

SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS

SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS

METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...

METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...

METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...

STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP

INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES

Early Write Method and Apparatus

MEMORY REFRESH SYSTEM AND METHOD

METHOD AND APPARATUS FOR MODIFYING A BURST LENGTH FOR SEMICONDUCTOR...

Abbreviated Burst Data Transfers for Semiconductor Memory

Memory configured on a common substrate

MEMORY DEVICE WITH MULTIPLE CONFIGURATIONS

METHOD AND APPARATUS FOR CONTROLLING A SHARED BUS

ERROR CORRECTION IN MEMORY DEVICES

METHOD AND APPARATUS FOR COMMUNICATING COMMAND AND ADDRESS SIGNALS

METHOD AND CIRCUIT FOR TRANSMITTING A MEMORY CLOCK SIGNAL

Memory system

Method and apparatus for early write termination in a semiconducuto...

Shared interface for components in an embedded system

Latency circuit for semiconductor memories

Clock circuit for semiconductor memories

Technique to suppress bitline leakage current

Shared interface semiconductor memories

Technique to suppress leakage current

Dual-port semiconductor memories

Random access memory having ECC

Technique to read special mode register