Patent Application
20070171735
There are many types of dynamic random access memory (DRAM) systems, including single data rate (SDR) synchronous DRAM (SDRAM), double data rate (DDR) synchronous DRAM (SDRAM), and others. In DDR SDRAM, the read and write operations are synchronized to a system clock supplied by a host system that includes the DDR SDRAM. Operations in DDR SDRAM are performed on both the rising and falling edges of the system clock (in SDR, operations are only performed on a rising edge). DDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the DQs. A single read or write access for the DDR SDRAM effectively consists of a single 2n bit wide, one clock cycle data transfer at the internal memory array and two corresponding n bit wide, one half clock cycle data transfers at the DQs.
Read and write accesses to DDR SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an activate command, which is followed by a read or write command. The address bits registered coincident with the activate command are used to select the bank and row to be accessed. The address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access.
A Row Address Strobe (RAS) signal is used to latch in the row addresses for selected memory cells and initiate a row access during a read or write operation and a Column Address Strobe (CAS) signal is used to latch in the column addresses for selected memory cells and initiate a column access during a read or write operation. CAS latency is the time between the initialization of a read command and the data being available on the output pads or pins of a memory. CAS latency is specified in clock cycles. The delay between an activate command and the first read command is referred to as the RAS to CAS delay, and this timing requirement is called tRCD.
Some types of DRAM devices, such as DDR SDRAM, typically have a minimum CAS latency of two or more clock cycles. Others, such as DDR2 SDRAM, can double the CAS latency and clock cycles. In any event, tRCD in DDR SDRAM cannot be shorter than a minimum time, or the memory circuit may fail. As such, additive latency (AL) is introduced to a read command, and added to tRCD in order to make the command assertion more flexible. Introduction of AL in some instances, however, becomes overhead to read or write latency if a read or write command is asserted after tRCD is satisfied.
For these and other reasons, there is a need for the present invention.
One embodiment of the present invention provides a random access memory. The random access memory includes an array of memory cells, a mode register and a controller. The mode register is configured to hold a programmable minimum timing requirement. The controller is configured to retrieve the programmable minimum timing requirement and to access the array of memory cells in a double data rate prefetch mode in response to a read command after the programmable minimum timing requirement is met.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Conductive word lines 34, referred to as row select lines, extend in the x-direction across the array of memory cells 32. Conductive bit lines 36, referred to as column select lines, extend in the y-direction across the array of memory cells 32. A memory cell 38 is located at each cross point of a word line 34 and a bit line 36. Each word line 34 is electrically coupled to row decoder 40 and each bit line 36 is electrically coupled to a sense amplifier 42. The sense amplifiers 42 are electrically coupled to column decoder 44 through conductive column decoder lines 45 and to data in/out circuit 46 through data lines 47.
Data in/out circuit 46 includes a plurality of latches and data input/output (I/O) pads or pins (DQs) to transfer data between memory bank 30 and an external device. In one embodiment, there is one data in/out circuit 46 for all memory banks. In another embodiment, there is one data in/out circuit 46 for every memory bank or groups of memory banks. Data written into memory bank 30 is presented as voltages on the DQs from an external device. The voltages are translated into the appropriate logic levels and stored in selected memory cells 38. Data read from memory bank 30 is presented by memory bank 30 on the DQs for an external device to retrieve. Data read from selected memory cells 38 appears at the DQs once access is complete and the output is enabled. At other times, the DQs are in a high impedance state.
Data in/out circuit 46 includes a first in/first out (FIFO) memory block and a bypass around the FIFO memory block. The bypass is electrically coupled between the data lines 47 and each DQ. During a read operation, data passes through the FIFO memory block for a column address strobe (CAS) latency greater than one and through the bypass around the FIFO memory block for a CAS latency of one.
Memory controller 20 controls reading data from and writing data to memory bank 30. During a read operation, memory controller 20 passes the row address of a selected memory cell or cells 38 to row decoder 40. Row decoder 40 activates the selected word line 34. As the selected word line 34 is activated, the value stored in each memory cell 38 coupled to the selected word line 34 is passed to the respective bit line 36. The value of each memory cell 38 is read by a sense amplifier 42 electrically coupled to the respective bit line 36. Memory controller 20 passes a column address of the selected memory cell or cells 38 to column decoder 44. Column decoder 44 selects which sense amplifiers 42 pass data to data in/out circuit 46 for retrieval by an external device.
During a write operation, the data to be stored in array 32 is placed in data in/out circuit 46 by an external device. Memory controller 20 passes the row address for the selected memory cell or cells 38 where the data is to be stored to row decoder 40. Row decoder 40 activates the selected word line 34. Memory controller 20 passes the column address for the selected memory cell or cells 38 where the data is to be stored to column decoder 44. Column decoder 44 selects which sense amplifiers 42 are passed the data from data in/out circuit 46. Sense amplifiers 42 write the data to the selected memory cell or cells 38 through bit lines 36.
In DDR SDRAM, the read and write operations are synchronized to a system clock. The system clock is supplied by a host system that includes the memory 10. DDR SDRAM operates from a differential clock, CK and bCK. The crossing of CK going high and bCK going low is referred to as the positive edge of CK. Commands such as read and write operations, including address and control signals, are registered at the positive edge of CK. Operations are performed on both the rising and falling edges of the system clock.
The DDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the DQs. A single read or write access for the DDR SDRAM effectively consists of a single 2n bit wide, one clock cycle data transfer at the internal memory array and two corresponding n bit wide, one half clock cycle data transfers at the DQs.
A bidirectional data strobe (DQS) is transmitted along with data for use in data capture at data in/out circuit 46. DQS is a strobe transmitted by the DDR SDRAM during read operations and by the memory controller, such as memory controller 20, during write operations. DQS is edge aligned with data for read operations and center aligned with data for write operations. Input and output data is registered on both edges of DQS.
Read and write accesses to the DDR SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an active command, which is followed by a read or write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed. The address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access.
A DDR-II SDRAM has the same features as a DDR SDRAM, except that the data rate is doubled. The DDR-II SDRAM architecture is essentially a 4n prefetch architecture with an interface designed to transfer four data words per clock cycle at the DQs. A single read or write access for the DDR-II SDRAM effectively consists of a single 4n bit wide, one clock cycle data transfer at the internal memory array and four corresponding n bit wide, one quarter clock cycle data transfers at the DQs. In one embodiment, memory 10 is a DDR-II SDRAM.
In a DDR-II SDRAM architecture without AL, activate commands (ACT) and read commands (RD) will be separated in some instances by dead clock cycles in order to assure that tRCD is met. This can lead to gaps in data output. With AL, however, subsequent read commands can be suspended internally by the period of the AL. In this way, memory controller 20 has more freedom in issuing active commands.
Although AL improves the flexibility and efficiency of memory controller 20, the introduction of AL in some instances, however, becomes overhead to read or write latency if a read or write command is asserted after tRCD is satisfied. In other words, if tRCD is already satisfied, adding AL after each subsequent read command becomes unnecessary penalty or delay to the system.
In this way, one embodiment of the present invention provides a variable or programmable tRCD that allows memory 10 to eliminate AL, but at that same time also prevent system errors that can arise from back-to-back active commands. In one embodiment, tRCD is applied at each active command for a variable number of clock cycles dependant on the clock frequency. In this way, no AL is needed on each subsequent read or write command after tRCD is satisfied. This reduces overhead while still providing increased flexibility and efficiency of memory 10.
In one embodiment, the variable tRCD is calculated as the number of clock cycles between memory controller 20 and memory bank 30. In one case, a programmable mode register (MR_CK) is provided within memory 10. In this way, memory controller 20 programs the clock cycle time of the operation into mode register MR_CK and based on this, the memory can read out a corresponding number of clock cycles for tRCD from the mode register (MR_CK).
As such, once programmable mode register (MR_CK) is set with the appropriate value according to the system requirements, controller 20 no longer uses AL. Instead, each time an active command (ACT) is sent, the tRCD value associated with the programmable mode register (MR_CK) is issued. Any read/write commands that are received during the tRCD cycles are then suspended until the tRCD is complete. In this way, controller 20 has the flexibility of allowing back-to-back commands without causing undue overhead by using AL with each read command.
In another embodiment, the variable tRCD is directly programmed into a mode register (MR_RCD) as a number of cycles.
One embodiment of a signal generating circuit 50 is illustrated in
In operation, command decoder 60 receives the command signals from controller 20, such as bCS (bank column select), bRAS (bank row address strobe), bCAS(bank column address strobe), and bWE (bank write enable). Decoder 62 receives the bank active signal (BA). When the bank active (BA) is triggered and ACT is high (from command decoder 60), and a bank is selected (at decoder 62), then the BK_ADD<i> signal from AND logic gate 64 is high. The BK_ADD<i> signal is received by and sets tRCD counter 66. As such, tRCD counter 66 starts to count by the number of clock cycles (CLK).
Then, at compare logic 68, the output of tRCD counter 66 is then compared against the tRCD signal from tRCD selector 72, which is in one embodiment selected from the clock signal stored in mode register 70 (as described above with reference to
The output from compare logic 68 is thus a signal indicating that tRCD has been met (Met_tRCD<i> signal). The Met_tRCD<i> signal will transition high when the number of clock cycles stored for the tRCD signal in mode register 70 is met by tRCD counter 66. The Met_tRCD<i> signal is then supplied to command register 74 to trigger bank read (Bk_rd<i>) and bank write (Bk_wt<i>) signals. When the Met_tRCD<i> signal is low, indicating that tRCD is still not met, command register 74 continues to suspend Bk_rd<i> and Bk_wt<i> signals.
As illustrated in
In the examples of the embodiments of the invention illustrated in
By contrast, in
In one embodiment of the present invention, controller 20 tracks or counts RL when a read command is issued before tRCD is met. As such, the total RL in that case will be the number of clock cycles remaining until tRCD is met plus the number of clock cycles in CL. Otherwise, RL is equal to CL in those cases where tRCD is already met.
In accordance with one embodiment of the present invention, read or write commands can be issued before the tRCD requirement is met without causing error. Within memory bank 30, a circuit, such as signal generating circuit 50, the invention uses a counter circuit to issue read or write command as soon as tRCD requirement to the specific bank is met. This effectively places part of command queue inside memory bank 30. In this way, controller 20 is freed from the limitation of tracking whether tRCD has been met for any particular bank. This increases the efficiency of controller 20 and improves the bus utilization without any access penalty, such as AL.
In the case of operation (a), once the CLK is stabilized its frequency is stored in the mode register (MR_CK) at 84, as described above with reference to
In the case of operation (b) once the CLK is stabilized tRCD is stored in the mode register (MR_tRCD) at 94, as described above with reference to
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
