Joseph Weiyeh Ku

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Printed circuit board with RFID antenna
- Patent number 7,432,816
- Issue date Oct 7, 2008
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed memory device providing adequate charging time for selec...
- Patent number 7,248,518
- Issue date Jul 24, 2007
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
Storing configuration information and a service record for an item...
- Patent number 7,183,924
- Issue date Feb 27, 2007
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for thermally assisted testing of integrated c...
- Patent number 7,087,439
- Issue date Aug 8, 2006
- Hewlett-Packard Development Company, L.P.
- Joseph Weiyeh Ku
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for building up large scale on chip de-couplin...
- Patent number 6,982,197
- Issue date Jan 3, 2006
- Hewlett-Packard Development Company, L.P.
- Joseph W. Ku
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for precharging word and bit lines for selecting memory cell...
- Patent number 6,940,770
- Issue date Sep 6, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for chip testing
- Patent number 6,910,155
- Issue date Jun 21, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Weiyeh Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
Minimizing power consumption in pipelined circuit by shutting down...
- Patent number 6,907,534
- Issue date Jun 14, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital event sampling circuit and method
- Patent number 6,889,349
- Issue date May 3, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Weiyeh Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Field repairable embedded memory in system-on-a-chip
- Patent number 6,886,117
- Issue date Apr 26, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip multiprocessor with multiple operating systems
- Patent number 6,874,014
- Issue date Mar 29, 2005
- Hewlett-Packard Development Company, L.P.
- Stephen E. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained thermal control in memory subsystems
- Patent number 6,851,064
- Issue date Feb 1, 2005
- Hewlett-Packard Development Company, L.P.
- Joseph Weiyeh Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power logic gate
- Patent number 6,826,112
- Issue date Nov 30, 2004
- Hewlett-Packard Development Company, L.P.
- Joseph Ku
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Analog method and circuit for monitoring digital events performance
- Patent number 6,600,328
- Issue date Jul 29, 2003
- Hewlett-Packard Development Company, L.P.
- Joseph Weiyeh Ku
- G01 - MEASURING TESTING
Information Patent Grant
High-density low-cost read-only memory circuit
- Patent number 6,504,746
- Issue date Jan 7, 2003
- Hewlett-Packard Company
- Joseph Weiyeh Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
Power efficient and high performance flip-flop
- Patent number 6,492,854
- Issue date Dec 10, 2002
- Hewlett-Packard Company
- Joseph Ku
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed output driver with an impedance adjustment scheme
- Patent number 6,351,172
- Issue date Feb 26, 2002
- Dmel Inc.
- Paul H. Ouyang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Over-current protection circuit for linear voltage regulators
- Patent number 6,347,029
- Issue date Feb 12, 2002
- Dmel, Inc.
- Paul H. Ouyang
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Power management using a pre-determined thermal characteristic of a...
- Publication number 20050246558
- Publication date Nov 3, 2005
- Joseph W. Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for selecting memory cells within a memory array
- Publication number 20050232023
- Publication date Oct 20, 2005
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for thermally assisted testing of integrated c...
- Publication number 20050054125
- Publication date Mar 10, 2005
- Joseph Weiyeh Ku
- G01 - MEASURING TESTING
Information Patent Application
Low power logic gate
- Publication number 20040141400
- Publication date Jul 22, 2004
- Joseph Ku
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for selecting memory cells within a memory array
- Publication number 20040141393
- Publication date Jul 22, 2004
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for building up large scale on chip de-couplin...
- Publication number 20030148578
- Publication date Aug 7, 2003
- Joseph W. Ku
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Field repairable embedded memory in system-on-a-chip
- Publication number 20030097627
- Publication date May 22, 2003
- Joseph Ku
- G11 - INFORMATION STORAGE
Information Patent Application
Digital event sampling circuit and method
- Publication number 20030046627
- Publication date Mar 6, 2003
- Joseph Weiyeh Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Fine-grained thermal control in memory subsystems
- Publication number 20030041289
- Publication date Feb 27, 2003
- Joseph Weiyeh Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Analog method and circuit for monitoring digital events performance
- Publication number 20030038643
- Publication date Feb 27, 2003
- Joseph Weiyeh Ku
- G01 - MEASURING TESTING
Information Patent Application
Power management for a pipelined circuit
- Publication number 20030005340
- Publication date Jan 2, 2003
- Joseph Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for chip testing
- Publication number 20020199136
- Publication date Dec 26, 2002
- Joseph Weiyeh Ku
- G01 - MEASURING TESTING
Information Patent Application
Chip multiprocessor with multiple operating systems
- Publication number 20020184328
- Publication date Dec 5, 2002
- Stephen E. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-density low-cost read-only memory circuit
- Publication number 20020184433
- Publication date Dec 5, 2002
- Joseph Weiyeh Ku
- H01 - BASIC ELECTRIC ELEMENTS

Joseph Weiyeh Ku

Person

Patents Grantslast 30 patents

Printed circuit board with RFID antenna

Self-timed memory device providing adequate charging time for selec...

Storing configuration information and a service record for an item...

Method and apparatus for thermally assisted testing of integrated c...

Method and apparatus for building up large scale on chip de-couplin...

Method for precharging word and bit lines for selecting memory cell...

System and method for chip testing

Minimizing power consumption in pipelined circuit by shutting down...

Digital event sampling circuit and method

Field repairable embedded memory in system-on-a-chip

Chip multiprocessor with multiple operating systems

Fine-grained thermal control in memory subsystems

Low power logic gate

Analog method and circuit for monitoring digital events performance

High-density low-cost read-only memory circuit

Power efficient and high performance flip-flop

High-speed output driver with an impedance adjustment scheme

Over-current protection circuit for linear voltage regulators

Patents Applicationslast 30 patents

Power management using a pre-determined thermal characteristic of a...

Method and apparatus for selecting memory cells within a memory array

Method and apparatus for thermally assisted testing of integrated c...

Low power logic gate

Method and apparatus for selecting memory cells within a memory array

Method and apparatus for building up large scale on chip de-couplin...

Field repairable embedded memory in system-on-a-chip

Digital event sampling circuit and method

Fine-grained thermal control in memory subsystems

Analog method and circuit for monitoring digital events performance

Power management for a pipelined circuit

System and method for chip testing

Chip multiprocessor with multiple operating systems

High-density low-cost read-only memory circuit