Joshua B. Fryman

Person

Corvallis, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache support for indirect loads and indirect stores in graph appli...
- Patent number 12,204,901
- Issue date Jan 21, 2025
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and methods for direct memory access instruction set arch...
- Patent number 12,158,852
- Issue date Dec 3, 2024
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for user space object coherency in a p...
- Patent number 11,960,922
- Issue date Apr 16, 2024
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system architecture for multi-threaded processors
- Patent number 11,630,691
- Issue date Apr 18, 2023
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage architectures for graph analysis applications
- Patent number 11,526,483
- Issue date Dec 13, 2022
- Intel Corporation
- Stijn Eyerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreaded processor core with hardware-assisted task scheduling
- Patent number 11,360,809
- Issue date Jun 14, 2022
- Intel Corporation
- William Paul Griffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory rank design for a memory channel that is optimized for graph...
- Patent number 11,308,006
- Issue date Apr 19, 2022
- Intel Corporation
- Byoungchan Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system architecture for multi-threaded processors
- Patent number 11,106,494
- Issue date Aug 31, 2021
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for barrier synchronization in a multi...
- Patent number 11,061,742
- Issue date Jul 13, 2021
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array broadcast and reduction systems and methods
- Patent number 10,983,793
- Issue date Apr 20, 2021
- Intel Corporation
- Joshua Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for dynamic automatic sub-cacheline gr...
- Patent number 10,942,851
- Issue date Mar 9, 2021
- Intel Corporation
- Wim Heirman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for ISA support for indirect loads and stores f...
- Patent number 10,929,132
- Issue date Feb 23, 2021
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor system with configurable cache sub-domains and cros...
- Patent number 10,795,819
- Issue date Oct 6, 2020
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect memory fetcher
- Patent number 10,684,858
- Issue date Jun 16, 2020
- Intel Corporation
- Stijn Eyerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for efficiently implementing a processor pipeline
- Patent number 10,409,763
- Issue date Sep 10, 2019
- Intel Corporation
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for low overhead control transfer to a...
- Patent number 10,296,338
- Issue date May 21, 2019
- Intel Corporation
- Brent R. Boswell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Collective communications apparatus and method for parallel systems
- Patent number 9,477,628
- Issue date Oct 25, 2016
- Intel Corporation
- Allan D. Knies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to provide failure detection
- Patent number 9,459,949
- Issue date Oct 4, 2016
- Intel Corporation
- Joshua Bruce Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable apparatus for hierarchical collective networks with...
- Patent number 9,405,724
- Issue date Aug 2, 2016
- Intel Corporation
- Jianping Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dishonest hardware policies
- Patent number 8,935,775
- Issue date Jan 13, 2015
- Intel Corporation
- Joshua Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to provide failure detection
- Patent number 8,832,505
- Issue date Sep 9, 2014
- Intel Corporation
- Joshua Bruce Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive optimized compare-exchange operation
- Patent number 8,601,242
- Issue date Dec 3, 2013
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptively handling remote atomic execution based upon contention p...
- Patent number 8,533,436
- Issue date Sep 10, 2013
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting scalable coherence on many-core...
- Patent number 8,312,225
- Issue date Nov 13, 2012
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting scalable coherence on many-core...
- Patent number 7,984,244
- Issue date Jul 19, 2011
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...
- Publication number 20250062278
- Publication date Feb 20, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNOLOGIES FOR PROCESSING PACKETS ON A NETWORK INTERFACE CONTROLL...
- Publication number 20240364643
- Publication date Oct 31, 2024
- Intel Corporation
- Sandeep K. Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHOTONIC INTEGRATED CIRCUIT PACKAGES WITH SCALABLE HETEROGENEOUS IN...
- Publication number 20240355980
- Publication date Oct 24, 2024
- Intel Corporation
- Daniel Klowden
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPUTING ARCHITECTURE
- Publication number 20240256283
- Publication date Aug 1, 2024
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS
- Publication number 20240241645
- Publication date Jul 18, 2024
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL EXTENSION TO GLOBAL ADDRESS SPACE AND SYSTEM SECURITY
- Publication number 20240160580
- Publication date May 16, 2024
- Intel Corporation
- Gurpreet Singh KALSI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY RECONFIGURABLE PROCESSING CORE
- Publication number 20240069921
- Publication date Feb 29, 2024
- Intel Corporation
- Scott Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED...
- Publication number 20240006375
- Publication date Jan 4, 2024
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH IN...
- Publication number 20230420411
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...
- Publication number 20230420409
- Publication date Dec 28, 2023
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-PHOTONICS PARALLEL DATA TRANSMISSION FABRIC AND INTERCONNECT
- Publication number 20230299851
- Publication date Sep 21, 2023
- Intel Corporation
- Joshua B. FRYMAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR CHIP-TO-CHIP OPTICAL DATA TRANSFER BACKGROUND
- Publication number 20230204819
- Publication date Jun 29, 2023
- Intel Corporation
- Khaled Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-MONOLITHIC DATA COMMUNICATION SYSTEM
- Publication number 20230097800
- Publication date Mar 30, 2023
- Intel Corporation
- Joshua Bruce Fryman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CACHE SUPPORT FOR INDIRECT LOADS AND INDIRECT STORES IN GRAPH APPLI...
- Publication number 20220413855
- Publication date Dec 29, 2022
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY AND METHODS FOR DIRECT MEMORY ACCESS INSTRUCTION SET ARCH...
- Publication number 20220414038
- Publication date Dec 29, 2022
- Intel Corporation
- ROBERT PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY AND HIGHLY PROGRAMMABLE INTERRUPT CONTROLLER UNIT
- Publication number 20220229795
- Publication date Jul 21, 2022
- Scott N. Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW OVERHEAD ERROR CORRECTION CODE
- Publication number 20220229723
- Publication date Jul 21, 2022
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATING NETWORK FLOW CONTROL
- Publication number 20220224605
- Publication date Jul 14, 2022
- Intel Corporation
- Samkit Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INSTRUCTION SET ARCHITECTURE WITH PROGRAMMABLE DIRECT MEMORY ACCESS...
- Publication number 20220222075
- Publication date Jul 14, 2022
- Robert S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL MEMORY MODEL FOR DISTRIBUTED FUNCTIONAL SIMULATIONS
- Publication number 20220222397
- Publication date Jul 14, 2022
- Intel Corporation
- Samkit Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE-SCALE MATRIX RESTRUCTURING AND MATRIX-SCALAR OPERATIONS
- Publication number 20220100508
- Publication date Mar 31, 2022
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR USER SPACE OBJECT COHERENCY IN A P...
- Publication number 20220091987
- Publication date Mar 24, 2022
- Intel Corporation
- JOSHUA B. FRYMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-NETWORK MULTICAST OPERATIONS
- Publication number 20210409265
- Publication date Dec 30, 2021
- Intel Corporation
- Robert PAWLOWSKI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY SYSTEM ARCHITECTURE FOR MULTI-THREADED PROCESSORS
- Publication number 20210389984
- Publication date Dec 16, 2021
- Intel Corporation
- Robert PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE SUPPORT FOR DUAL-MEMORY ATOMIC OPERATIONS
- Publication number 20200401412
- Publication date Dec 24, 2020
- Intel Corporation
- Robert PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARRAY BROADCAST AND REDUCTION SYSTEMS AND METHODS
- Publication number 20200310795
- Publication date Oct 1, 2020
- Intel Corporation
- Joshua Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY RANK DESIGN FOR A MEMORY CHANNEL THAT IS OPTIMIZED FOR GRAPH...
- Publication number 20200233819
- Publication date Jul 23, 2020
- Intel Corporation
- Byoungchan OH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Dynamic Automatic Sub-Cacheline Gr...
- Publication number 20200174929
- Publication date Jun 4, 2020
- Intel Corporation
- Wim HEIRMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM ARCHITECTURE FOR MULTI-THREADED PROCESSORS
- Publication number 20200104164
- Publication date Apr 2, 2020
- Intel Corporation
- Robert PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR BARRIER SYNCHRONIZATION IN A MULTI...
- Publication number 20200004602
- Publication date Jan 2, 2020
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING

Joshua B. Fryman

Person

Patents Grantslast 30 patents

Cache support for indirect loads and indirect stores in graph appli...

Circuitry and methods for direct memory access instruction set arch...

System, apparatus and method for user space object coherency in a p...

Memory system architecture for multi-threaded processors

Storage architectures for graph analysis applications

Multithreaded processor core with hardware-assisted task scheduling

Memory rank design for a memory channel that is optimized for graph...

Memory system architecture for multi-threaded processors

System, apparatus and method for barrier synchronization in a multi...

Array broadcast and reduction systems and methods

System, apparatus and method for dynamic automatic sub-cacheline gr...

Systems and methods for ISA support for indirect loads and stores f...

Multi-processor system with configurable cache sub-domains and cros...

Indirect memory fetcher

Apparatus and method for efficiently implementing a processor pipeline

System, apparatus and method for low overhead control transfer to a...

Collective communications apparatus and method for parallel systems

Methods and apparatus to provide failure detection

Reconfigurable apparatus for hierarchical collective networks with...

Method and apparatus for dishonest hardware policies

Methods and apparatus to provide failure detection

Adaptive optimized compare-exchange operation

Adaptively handling remote atomic execution based upon contention p...

Method and apparatus for supporting scalable coherence on many-core...

Method and apparatus for supporting scalable coherence on many-core...

Patents Applicationslast 30 patents

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...

TECHNOLOGIES FOR PROCESSING PACKETS ON A NETWORK INTERFACE CONTROLL...

PHOTONIC INTEGRATED CIRCUIT PACKAGES WITH SCALABLE HETEROGENEOUS IN...

COMPUTING ARCHITECTURE

INSTRUCTION SET ARCHITECTURE AND HARDWARE SUPPORT FOR HASH OPERATIONS

VIRTUAL EXTENSION TO GLOBAL ADDRESS SPACE AND SYSTEM SECURITY

DYNAMICALLY RECONFIGURABLE PROCESSING CORE

PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED...

PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH IN...

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT D...

MICRO-PHOTONICS PARALLEL DATA TRANSMISSION FABRIC AND INTERCONNECT

TECHNOLOGIES FOR CHIP-TO-CHIP OPTICAL DATA TRANSFER BACKGROUND

PSEUDO-MONOLITHIC DATA COMMUNICATION SYSTEM

CACHE SUPPORT FOR INDIRECT LOADS AND INDIRECT STORES IN GRAPH APPLI...

CIRCUITRY AND METHODS FOR DIRECT MEMORY ACCESS INSTRUCTION SET ARCH...

LOW LATENCY AND HIGHLY PROGRAMMABLE INTERRUPT CONTROLLER UNIT

LOW OVERHEAD ERROR CORRECTION CODE

SIMULATING NETWORK FLOW CONTROL

INSTRUCTION SET ARCHITECTURE WITH PROGRAMMABLE DIRECT MEMORY ACCESS...

PARALLEL MEMORY MODEL FOR DISTRIBUTED FUNCTIONAL SIMULATIONS

LARGE-SCALE MATRIX RESTRUCTURING AND MATRIX-SCALAR OPERATIONS

SYSTEM, APPARATUS AND METHOD FOR USER SPACE OBJECT COHERENCY IN A P...

IN-NETWORK MULTICAST OPERATIONS

MEMORY SYSTEM ARCHITECTURE FOR MULTI-THREADED PROCESSORS

HARDWARE SUPPORT FOR DUAL-MEMORY ATOMIC OPERATIONS

ARRAY BROADCAST AND REDUCTION SYSTEMS AND METHODS

MEMORY RANK DESIGN FOR A MEMORY CHANNEL THAT IS OPTIMIZED FOR GRAPH...

System, Apparatus And Method For Dynamic Automatic Sub-Cacheline Gr...

MEMORY SYSTEM ARCHITECTURE FOR MULTI-THREADED PROCESSORS

SYSTEM, APPARATUS AND METHOD FOR BARRIER SYNCHRONIZATION IN A MULTI...