Ju Shen

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Simultaneous switching output noise estimation and reduction system...
- Patent number 7,895,555
- Issue date Feb 22, 2011
- Lattice Semiconductor Corporation
- Chris West
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register data retention systems and methods during reprogramming of...
- Patent number 7,876,125
- Issue date Jan 25, 2011
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and devices for storing a security key using programmable fuses
- Patent number 7,834,652
- Issue date Nov 16, 2010
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input/output placement systems and methods to reduce simultaneous s...
- Patent number 7,788,620
- Issue date Aug 31, 2010
- Lattice Semiconductor Corporation
- Hua Xue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for storing a security key using programmable f...
- Patent number 7,675,313
- Issue date Mar 9, 2010
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfiguration of programmable logic devices
- Patent number 7,652,500
- Issue date Jan 26, 2010
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,573,291
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Register data retention systems and methods during reprogramming of...
- Patent number 7,535,253
- Issue date May 19, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfiguration of programmable logic devices
- Patent number 7,375,549
- Issue date May 20, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,327,160
- Issue date Feb 5, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,295,035
- Issue date Nov 13, 2007
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,208,975
- Issue date Apr 24, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Macrocells supporting a carry cascade
- Patent number 6,915,323
- Issue date Jul 5, 2005
- Lattice Semiconductor Corporation
- Jason Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced wide input product term cas...
- Patent number 6,903,573
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile and reconfigurable programmable logic devices
- Patent number 6,828,823
- Issue date Dec 7, 2004
- Lattice Semiconductor Corporation
- Cyrus Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FIFO memory architecture
- Patent number 6,777,979
- Issue date Aug 17, 2004
- Lattice Semiconductor Corporation
- Jinghui Zhu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method with generic logic blocks
- Patent number 6,765,408
- Issue date Jul 20, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic array including lookup table means for generatin...
- Patent number 6,567,969
- Issue date May 20, 2003
- Lattice Semiconductor Corporation
- Om Prakash Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,462,576
- Issue date Oct 8, 2002
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and structure dynamic in-system programming
- Patent number 6,356,107
- Issue date Mar 12, 2002
- Lattice Semiconductor Corporation
- Howard Y. M. Tang
- G01 - MEASURING TESTING
Information Patent Grant
Method and structure for dynamic in-system programming
- Patent number 6,304,099
- Issue date Oct 16, 2001
- Lattice Semiconductor Corporation
- Howard Y. M. Tang
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic device
- Patent number 6,294,925
- Issue date Sep 25, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for minimizing instantaneous currents when driving bus signals
- Patent number 6,278,311
- Issue date Aug 21, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,255,847
- Issue date Jul 3, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit device with slew control and skew c...
- Patent number 6,229,336
- Issue date May 8, 2001
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,191,609
- Issue date Feb 20, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,133,750
- Issue date Oct 17, 2000
- Lattice Semiconductor Corp.
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic array including IOB to longlines interconnect me...
- Patent number 6,128,770
- Issue date Oct 3, 2000
- Vantis Corporation
- Om Prakash Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device
- Patent number 6,104,207
- Issue date Aug 15, 2000
- Lattice Semiconductor Corporation
- Albert Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable output voltage levels
- Patent number 6,066,977
- Issue date May 23, 2000
- Lattice Semiconductor Corporation
- Bradley Felton
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Device and method with generic logic blocks
- Publication number 20040000928
- Publication date Jan 1, 2004
- Lattice Semiconductor Corporation
- Jason Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Simultaneous switching output noise estimation and reduction system...

Register data retention systems and methods during reprogramming of...

Method and devices for storing a security key using programmable fuses

Input/output placement systems and methods to reduce simultaneous s...

Methods and systems for storing a security key using programmable f...

Reconfiguration of programmable logic devices

Programmable logic device with enhanced logic block architecture

Register data retention systems and methods during reprogramming of...

Reconfiguration of programmable logic devices

SERDES with programmable I/O architecture

Programmable logic device with enhanced logic block architecture

SERDES with programmable I/O architecture

Macrocells supporting a carry cascade

Programmable logic device with enhanced wide input product term cas...

Non-volatile and reconfigurable programmable logic devices

FIFO memory architecture

Device and method with generic logic blocks

Configurable logic array including lookup table means for generatin...

Programmable logic device

Method and structure dynamic in-system programming

Method and structure for dynamic in-system programming

Programmable logic device

Method for minimizing instantaneous currents when driving bus signals

Programmable logic device

Programmable integrated circuit device with slew control and skew c...

Combination of global clock and localized clocks

Combination of global clock and localized clocks

Configurable logic array including IOB to longlines interconnect me...

Programmable logic device

Programmable output voltage levels

Patents Applicationslast 30 patents

Device and method with generic logic blocks