Juergen Dirks

Person

Holzkirchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Intelligent timing analysis and constraint generation GUI
- Patent number 8,863,053
- Issue date Oct 14, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing violation debugging inside place and route tool
- Patent number 8,584,068
- Issue date Nov 12, 2013
- LSI Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automation of tie cell insertion, optimization and replacement by s...
- Patent number 8,572,543
- Issue date Oct 29, 2013
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree insertion delay independent interface
- Patent number 8,564,337
- Issue date Oct 22, 2013
- LSI Corporation
- Stefan Block
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Intelligent timing analysis and constraint generation GUI
- Patent number 8,539,407
- Issue date Sep 17, 2013
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special engineering change order cells
- Patent number 8,332,801
- Issue date Dec 11, 2012
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating integrated circuit floorplan layouts
- Patent number 8,219,959
- Issue date Jul 10, 2012
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automation of tie cell insertion, optimization and replacement by s...
- Patent number 8,161,447
- Issue date Apr 17, 2012
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for configuring an integrated circuit d...
- Patent number 7,958,473
- Issue date Jun 7, 2011
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing violation debugging inside place and route tool
- Patent number 7,747,975
- Issue date Jun 29, 2010
- LSI Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special engineering change order cells
- Patent number 7,634,748
- Issue date Dec 15, 2009
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automation of tie cell insertion, optimization and replacement by s...
- Patent number 7,546,568
- Issue date Jun 9, 2009
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of flip flop initialization structures with respect to...
- Patent number 7,546,560
- Issue date Jun 9, 2009
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent timing analysis and constraint generation GUI
- Patent number 7,523,426
- Issue date Apr 21, 2009
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly RTL instructor for advanced DFT and design closure
- Patent number 7,441,210
- Issue date Oct 21, 2008
- LSI Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced standard cell power connection
- Patent number 7,398,489
- Issue date Jul 8, 2008
- LSI Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell builder for different layer stacks
- Patent number 7,334,206
- Issue date Feb 19, 2008
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Engineering change order scenario manager
- Patent number 7,331,028
- Issue date Feb 12, 2008
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing violation debugging inside place and route tool
- Patent number 7,325,215
- Issue date Jan 29, 2008
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special tie-high/low cells for single metal layer route changes
- Patent number 7,191,424
- Issue date Mar 13, 2007
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of a clock signal supply network during design of integra...
- Patent number 7,117,472
- Issue date Oct 3, 2006
- LSI Logic Corporation
- Stefan G. Auracher
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AN...
- Publication number 20160284392
- Publication date Sep 29, 2016
- GLOBALFOUNDRIES INC.
- Stefan Block
- G11 - INFORMATION STORAGE
Information Patent Application
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
- Publication number 20130346932
- Publication date Dec 26, 2013
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE
- Publication number 20120200322
- Publication date Aug 9, 2012
- LSI Corporation
- Stefan Block
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY S...
- Publication number 20120198407
- Publication date Aug 2, 2012
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay-Cell Footprint-Compatible Buffers
- Publication number 20110320997
- Publication date Dec 29, 2011
- LSI Corporation
- Farid Labib
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Write Through Speed Up for Memory Circuit
- Publication number 20110063926
- Publication date Mar 17, 2011
- LSI Corporation
- Stefan G. Block
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS
- Publication number 20110023000
- Publication date Jan 27, 2011
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
- Publication number 20100229141
- Publication date Sep 9, 2010
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL ENGINEERING CHANGE ORDER CELLS
- Publication number 20100050142
- Publication date Feb 25, 2010
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY S...
- Publication number 20090228855
- Publication date Sep 10, 2009
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
- Publication number 20090150846
- Publication date Jun 11, 2009
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT D...
- Publication number 20080216035
- Publication date Sep 4, 2008
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of flip flop initialization structures with respect to...
- Publication number 20080141184
- Publication date Jun 12, 2008
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
- Publication number 20080077903
- Publication date Mar 27, 2008
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device for analyzing log files generated by process automation tools
- Publication number 20070204215
- Publication date Aug 30, 2007
- LSI Logic Corporation
- Norbert Mueller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automation of tie cell insertion, optimization and replacement by s...
- Publication number 20070143725
- Publication date Jun 21, 2007
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-the-fly RTL instructor for advanced DFT and design closure
- Publication number 20070083839
- Publication date Apr 12, 2007
- LSI Logic Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing violation debugging inside place and route tool
- Publication number 20070050745
- Publication date Mar 1, 2007
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intelligent timing analysis and constraint generation GUI
- Publication number 20060230373
- Publication date Oct 12, 2006
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Advanced standard cell power connection
- Publication number 20060226530
- Publication date Oct 12, 2006
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell builder for different layer stacks
- Publication number 20060129962
- Publication date Jun 15, 2006
- LSI Logic Corporation
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Special tie-high/low cells for single metal layer route changes
- Publication number 20060048079
- Publication date Mar 2, 2006
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Special engineering change order cells
- Publication number 20060031798
- Publication date Feb 9, 2006
- LSI Logic Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Engineering change order scenario manager
- Publication number 20060026546
- Publication date Feb 2, 2006
- Matthias Dinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement of a clock signal supply network during design of integra...
- Publication number 20060010408
- Publication date Jan 12, 2006
- LSI Logic Corporation
- Stefan G. Auracher
- G06 - COMPUTING CALCULATING COUNTING

Juergen Dirks

Person

Patents Grantslast 30 patents

Intelligent timing analysis and constraint generation GUI

Timing violation debugging inside place and route tool

Automation of tie cell insertion, optimization and replacement by s...

Clock tree insertion delay independent interface

Intelligent timing analysis and constraint generation GUI

Special engineering change order cells

Generating integrated circuit floorplan layouts

Automation of tie cell insertion, optimization and replacement by s...

Method and computer program for configuring an integrated circuit d...

Timing violation debugging inside place and route tool

Special engineering change order cells

Automation of tie cell insertion, optimization and replacement by s...

Optimization of flip flop initialization structures with respect to...

Intelligent timing analysis and constraint generation GUI

On-the-fly RTL instructor for advanced DFT and design closure

Advanced standard cell power connection

Cell builder for different layer stacks

Engineering change order scenario manager

Timing violation debugging inside place and route tool

Special tie-high/low cells for single metal layer route changes

Placement of a clock signal supply network during design of integra...

Patents Applicationslast 30 patents

MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AN...

INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI

CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE

AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY S...

Delay-Cell Footprint-Compatible Buffers

Write Through Speed Up for Memory Circuit

GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS

TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL

SPECIAL ENGINEERING CHANGE ORDER CELLS

AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY S...

INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI

METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT D...

Optimization of flip flop initialization structures with respect to...

TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL

Device for analyzing log files generated by process automation tools

Automation of tie cell insertion, optimization and replacement by s...

On-the-fly RTL instructor for advanced DFT and design closure

Timing violation debugging inside place and route tool

Intelligent timing analysis and constraint generation GUI

Advanced standard cell power connection

Cell builder for different layer stacks

Special tie-high/low cells for single metal layer route changes

Special engineering change order cells

Engineering change order scenario manager

Placement of a clock signal supply network during design of integra...