Kameswara K. Rao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automatic refresh for improving data retention and endurance charac...
- Patent number 8,161,355
- Issue date Apr 17, 2012
- MoSys, Inc.
- Stephen Fung
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling unused/inactive resources in an integrated circuit for st...
- Patent number 8,099,691
- Issue date Jan 17, 2012
- Xilinx, Inc.
- Tim Tuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two bits per cell non-volatile memory architecture
- Patent number 8,081,521
- Issue date Dec 20, 2011
- MoSys, Inc.
- Chee T. Chua
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and mechanism for controlling power consumption of an integr...
- Patent number 7,581,124
- Issue date Aug 25, 2009
- Xilinx, Inc.
- Neil G. Jacobson
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling unused/inactive resources in programmable logic devices f...
- Patent number 7,562,332
- Issue date Jul 14, 2009
- Xilinx, Inc.
- Tim Tuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tuning programmable logic devices for low-power design implementation
- Patent number 7,549,139
- Issue date Jun 16, 2009
- Xilinx, Inc.
- Tim Tuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Regulating unused/inactive resources in programmable logic devices...
- Patent number 7,504,854
- Issue date Mar 17, 2009
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitstream for configuring a PLD with encrypted design data
- Patent number 7,117,373
- Issue date Oct 3, 2006
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disabling unused/inactive resources in programmable logic devices f...
- Patent number 7,098,689
- Issue date Aug 29, 2006
- Xilinx, Inc.
- Tim Tuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Series capacitor coupling multiplexer for programmable logic devices
- Patent number 7,046,071
- Issue date May 16, 2006
- Xilinx, Inc.
- Robert O. Conn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with decryption algorithm and decryption key
- Patent number 6,931,543
- Issue date Aug 16, 2005
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,549,458
- Issue date Apr 15, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,522,582
- Issue date Feb 18, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy architecture and method for non-volatile storage
- Patent number 6,438,065
- Issue date Aug 20, 2002
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile/battery-backed key in PLD
- Patent number 6,366,117
- Issue date Apr 2, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming a two transistor flash EPROM cell
- Patent number 6,265,266
- Issue date Jul 24, 2001
- Xilinx, Inc.
- Anders T. Dejenfelt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture for non-volatile storage using gate breakdown s...
- Patent number 6,243,294
- Issue date Jun 5, 2001
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
One-time programmable poly-fuse circuit for implementing non-volati...
- Patent number 6,208,549
- Issue date Mar 27, 2001
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage charge pump using standard sub 0.35 micron CMOS process
- Patent number 6,177,830
- Issue date Jan 23, 2001
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder for a non-volatile memory array using gate breakdown struct...
- Patent number 6,055,205
- Issue date Apr 25, 2000
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array using gate breakdown structure in standar...
- Patent number 6,044,012
- Issue date Mar 28, 2000
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Overridable data protection mechanism for PLDs
- Patent number 5,991,880
- Issue date Nov 23, 1999
- Xilinx, Inc.
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory array using single poly EEPROM in standard CMOS...
- Patent number 5,959,885
- Issue date Sep 28, 1999
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array using gate breakdown structure
- Patent number 5,949,712
- Issue date Sep 7, 1999
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient in-system programming structure and method for non-volati...
- Patent number 5,949,987
- Issue date Sep 7, 1999
- Xilinx, Inc.
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two transistor flash EPROM cell
- Patent number 5,914,514
- Issue date Jun 22, 1999
- Xilinx, Inc.
- Anders T. Dejenfelt
- G11 - INFORMATION STORAGE
Information Patent Grant
Overridable data protection mechanism for PLDs
- Patent number 5,838,901
- Issue date Nov 17, 1998
- Xilinx, Inc.
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile storage for standard CMOS integrated circuits
- Patent number 5,835,402
- Issue date Nov 10, 1998
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for partially reprogramming an operational programmable log...
- Patent number 5,764,076
- Issue date Jun 9, 1998
- Xilinx, Inc.
- Napoleon W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient in-system programming structure and method for non-volati...
- Patent number 5,734,868
- Issue date Mar 31, 1998
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Two Bits Per Cell Non-Volatile Memory Architecture
- Publication number 20100208530
- Publication date Aug 19, 2010
- MOSYS, INC.
- Chee T. Chua
- G11 - INFORMATION STORAGE
Information Patent Application
Automatic refresh for improving data retention and endurance charac...
- Publication number 20100205504
- Publication date Aug 12, 2010
- MOSYS, INC.
- Stephen Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double Polysilicon Process for Non-Volatile Memory
- Publication number 20100140680
- Publication date Jun 10, 2010
- MOSYS, INC.
- Jeong Y. Choi
- H01 - BASIC ELECTRIC ELEMENTS

Kameswara K. Rao

Person

Patents Grantslast 30 patents

Automatic refresh for improving data retention and endurance charac...

Disabling unused/inactive resources in an integrated circuit for st...

Two bits per cell non-volatile memory architecture

Method and mechanism for controlling power consumption of an integr...

Disabling unused/inactive resources in programmable logic devices f...

Tuning programmable logic devices for low-power design implementation

Regulating unused/inactive resources in programmable logic devices...

Bitstream for configuring a PLD with encrypted design data

Disabling unused/inactive resources in programmable logic devices f...

Series capacitor coupling multiplexer for programmable logic devices

Programmable logic device with decryption algorithm and decryption key

Non-volatile memory array using gate breakdown structures

Non-volatile memory array using gate breakdown structures

Redundancy architecture and method for non-volatile storage

Nonvolatile/battery-backed key in PLD

Method of forming a two transistor flash EPROM cell

Memory architecture for non-volatile storage using gate breakdown s...

One-time programmable poly-fuse circuit for implementing non-volati...

High voltage charge pump using standard sub 0.35 micron CMOS process

Decoder for a non-volatile memory array using gate breakdown struct...

Non-volatile memory array using gate breakdown structure in standar...

Overridable data protection mechanism for PLDs

Non-volatile memory array using single poly EEPROM in standard CMOS...

Non-volatile memory array using gate breakdown structure

Efficient in-system programming structure and method for non-volati...

Two transistor flash EPROM cell

Overridable data protection mechanism for PLDs

Non-volatile storage for standard CMOS integrated circuits

Circuit for partially reprogramming an operational programmable log...

Efficient in-system programming structure and method for non-volati...

Patents Applicationslast 30 patents

Two Bits Per Cell Non-Volatile Memory Architecture

Automatic refresh for improving data retention and endurance charac...

Double Polysilicon Process for Non-Volatile Memory