Kavitha Chaturvedula

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Control signal source replication
- Patent number 8,001,497
- Issue date Aug 16, 2011
- LSI Corporation
- Randall P. Fry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Statistical design closure
- Patent number 7,895,546
- Issue date Feb 22, 2011
- LSI Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing test code generation for verification environment
- Patent number 7,844,929
- Issue date Nov 30, 2010
- LSI Corporation
- Kavitha Chaturvedula
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced method of optimizing multiplex structures and multiplex co...
- Patent number 7,594,201
- Issue date Sep 22, 2009
- LSI Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing RTL code for multiplex structures
- Patent number 7,086,015
- Issue date Aug 1, 2006
- LSI Logic Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated analysis of RTL code containing ASIC vendor rules
- Patent number 7,082,584
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ADVANCED PHYSICAL SIMULATOR
- Publication number 20100217564
- Publication date Aug 26, 2010
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL SIGNAL SOURCE REPLICATION
- Publication number 20100083195
- Publication date Apr 1, 2010
- LSI Corporation
- Randall P. Fry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing test code generation for verification environment
- Publication number 20090282307
- Publication date Nov 12, 2009
- Kavitha Chaturvedula
- G01 - MEASURING TESTING
Information Patent Application
Statistical design closure
- Publication number 20090063564
- Publication date Mar 5, 2009
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for analysis of an integrated circuit d...
- Publication number 20070079266
- Publication date Apr 5, 2007
- LSI Logic Corporation
- Krishna Devineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CO...
- Publication number 20060282801
- Publication date Dec 14, 2006
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of optimizing RTL code for multiplex structures
- Publication number 20050257180
- Publication date Nov 17, 2005
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated analysis of RTL code containing ASIC vendor rules
- Publication number 20040221249
- Publication date Nov 4, 2004
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING

Kavitha Chaturvedula

Person

Patents Grantslast 30 patents

Control signal source replication

Statistical design closure

Optimizing test code generation for verification environment

Enhanced method of optimizing multiplex structures and multiplex co...

Method of optimizing RTL code for multiplex structures

Automated analysis of RTL code containing ASIC vendor rules

Patents Applicationslast 30 patents

ADVANCED PHYSICAL SIMULATOR

CONTROL SIGNAL SOURCE REPLICATION

Optimizing test code generation for verification environment

Statistical design closure

Method and computer program for analysis of an integrated circuit d...

ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CO...

Method of optimizing RTL code for multiplex structures

Automated analysis of RTL code containing ASIC vendor rules