Kedar Janardan Dhori

Person

Ghaziabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Bit-cell architecture based in-memory compute
- Patent number 12,183,424
- Issue date Dec 31, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive body bias management for an in-memory compute operation wh...
- Patent number 12,176,025
- Issue date Dec 24, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test circuit for segmented static random access memor...
- Patent number 12,170,120
- Issue date Dec 17, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Hitesh Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry for adjusting retention voltage of a static random access...
- Patent number 12,165,698
- Issue date Dec 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive bit line overdrive control for an in-memory compute operat...
- Patent number 11,984,151
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell layout including arrangement of multiple active regions a...
- Patent number 11,758,707
- Issue date Sep 12, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Shafquat Jahan Ahmed
Information Patent Grant
Computing system power management device, system and method
- Patent number 11,726,543
- Issue date Aug 15, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing read stability of a static rando...
- Patent number 10,224,097
- Issue date Mar 5, 2019
- STMicroelectronics International N.V.
- Ashish Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for enhancing read stability of a static rando...
- Patent number 9,940,997
- Issue date Apr 10, 2018
- STMicroelectronics International N.V.
- Ashish Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature compensated read assist circuit for a static random acc...
- Patent number 9,865,333
- Issue date Jan 9, 2018
- STMicroelectronics International N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for generating a sense amplifier enable signal with variabl...
- Patent number 9,685,209
- Issue date Jun 20, 2017
- STMicroelectronics International N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE
Information Patent Grant
Repair control logic for safe memories having redundant elements
- Patent number 9,208,040
- Issue date Dec 8, 2015
- STMicroelectronics International N.V.
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20240395319
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...
- Publication number 20240177769
- Publication date May 30, 2024
- STMicroelectronics International N.V.
- Promod KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...
- Publication number 20240143239
- Publication date May 2, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240069096
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071429
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071439
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH A STATIC RANDOM ACCE...
- Publication number 20240015945
- Publication date Jan 11, 2024
- STMicroelectronics S.A.
- Olivier Weber
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...
- Publication number 20230410892
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230410862
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...
- Publication number 20230386566
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230386565
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230386564
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20230350483
- Publication date Nov 2, 2023
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20230102492
- Publication date Mar 30, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...
- Publication number 20230012567
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20230008833
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230009329
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230012303
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230008275
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITRY FOR ADJUSTING RETENTION VOLTAGE OF A STATIC RANDOM ACCESS...
- Publication number 20220130454
- Publication date Apr 28, 2022
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS
- Publication number 20220122657
- Publication date Apr 21, 2022
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
LOWER POWER MEMORY WRITE OPERATION
- Publication number 20210327501
- Publication date Oct 21, 2021
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM LAYOUT WITH SMALL FOOTPRINT AND EFFICIENT ASPECT RATIO
- Publication number 20210193669
- Publication date Jun 24, 2021
- STMicroelectronics International N.V.
- Shafquat Jahan AHMED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20210181828
- Publication date Jun 17, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ENHANCING READ STABILITY OF A STATIC RANDO...
- Publication number 20180190346
- Publication date Jul 5, 2018
- STMicroelectronics International N.V.
- Ashish Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACC...
- Publication number 20170301396
- Publication date Oct 19, 2017
- STMicroelectronics International N.V
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE

Kedar Janardan Dhori

Person

Patents Grantslast 30 patents

Bit-cell architecture based in-memory compute

Adaptive body bias management for an in-memory compute operation wh...

Built-in self test circuit for segmented static random access memor...

Circuitry for adjusting retention voltage of a static random access...

Serial word line actuation with linked source voltage supply modula...

Adaptive bit line overdrive control for an in-memory compute operat...

SRAM cell layout including arrangement of multiple active regions a...

Computing system power management device, system and method

Method and apparatus for enhancing read stability of a static rando...

Method and apparatus for enhancing read stability of a static rando...

Temperature compensated read assist circuit for a static random acc...

Circuit for generating a sense amplifier enable signal with variabl...

Repair control logic for safe memories having redundant elements

Patents Applicationslast 30 patents

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

SILICON-ON-INSULATOR SEMICONDUCTOR DEVICE WITH A STATIC RANDOM ACCE...

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...

CIRCUITRY FOR ADJUSTING RETENTION VOLTAGE OF A STATIC RANDOM ACCESS...

DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS

LOWER POWER MEMORY WRITE OPERATION

SRAM LAYOUT WITH SMALL FOOTPRINT AND EFFICIENT ASPECT RATIO

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD

METHOD AND APPARATUS FOR ENHANCING READ STABILITY OF A STATIC RANDO...

TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACC...