Kenneth D. Wagner

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Edge-triggered scan flip-flop and one-pass scan synthesis methodology
- Patent number 6,389,566
- Issue date May 14, 2002
- S3 Incorporated
- Kenneth D. Wagner
- G01 - MEASURING TESTING
Information Patent Grant
Multiple input signature testing & diagnosis for embedded blocks in...
- Patent number 6,158,033
- Issue date Dec 5, 2000
- S3 Incorporated
- Kenneth D. Wagner
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing partial unscan and near full sc...
- Patent number 6,067,650
- Issue date May 23, 2000
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing partial unscan and near full sc...
- Patent number 5,696,771
- Issue date Dec 9, 1997
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Fault simulation of testing for board circuit failures
- Patent number 5,633,812
- Issue date May 27, 1997
- International Business Machines Corporation
- James S. Allen
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid pattern self-testing of integrated circuits
- Patent number 5,612,963
- Issue date Mar 18, 1997
- International Business Machines Corporation
- Bernd K. F. Koenemann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for memory dynamic burn-in and test
- Patent number 5,375,091
- Issue date Dec 20, 1994
- International Business Machines Corporation
- Robert W. Berry
- G11 - INFORMATION STORAGE

Kenneth D. Wagner

Person

Patents Grantslast 30 patents

Edge-triggered scan flip-flop and one-pass scan synthesis methodology

Multiple input signature testing & diagnosis for embedded blocks in...

Method and apparatus for performing partial unscan and near full sc...

Method and apparatus for performing partial unscan and near full sc...

Fault simulation of testing for board circuit failures

Hybrid pattern self-testing of integrated circuits

Method and apparatus for memory dynamic burn-in and test