Kenneth L. Williams

Person

Sherman, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to decode dual-tone signals
- Patent number 8,391,469
- Issue date Mar 5, 2013
- Texas Instruments Incorporated
- Steven Edward Marum
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for controlling operation of a light-emitting diode
- Patent number 7,701,152
- Issue date Apr 20, 2010
- Texas Instruments Incorporated
- Kenneth L Williams
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Linking addressable shadow port and protocol for serial bus networks
- Patent number 7,353,307
- Issue date Apr 1, 2008
- Texas Instruments Incorporated
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linking addressable shadow port and protocol for serial bus networks
- Patent number 7,177,965
- Issue date Feb 13, 2007
- Texas Instruments Incorporated
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linking addressable shadow port and protocol for serial bus networks
- Patent number 6,968,408
- Issue date Nov 22, 2005
- Texas Instruments Incorporated
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous FIFO memory having built-in self test logic
- Patent number 6,611,469
- Issue date Aug 26, 2003
- Texas Instruments Incorporated
- Kenneth L. Williams
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast FiFo memory storage system
- Patent number 6,366,529
- Issue date Apr 2, 2002
- Texas Instruments Incorporated
- Kenneth L. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast reprogrammable FIFO status flags system
- Patent number 6,345,008
- Issue date Feb 5, 2002
- Texas Instruments Incorporated
- Kenneth L. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access controller with split channel transfer capabil...
- Patent number 6,311,234
- Issue date Oct 30, 2001
- Texas Instruments Incorporated
- Natarajan Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA controller with split channel transfer capability and FIFO buff...
- Patent number 6,145,027
- Issue date Nov 7, 2000
- Texas Instruments Incorporated
- Natarajan Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential memory
- Patent number 5,594,700
- Issue date Jan 14, 1997
- Texas Instruments Incorporated
- Morris D. Ward
- G11 - INFORMATION STORAGE
Information Patent Grant
Fifo with fast retransmit mode
- Patent number 5,365,485
- Issue date Nov 15, 1994
- Texas Instruments Incorporated
- M. Dwayne Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First-in first-out memory
- Patent number 5,274,600
- Issue date Dec 28, 1993
- Texas Instruments Incorporated
- Morris D. Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential memory
- Patent number 5,255,242
- Issue date Oct 19, 1993
- Texas Instruments Incorporated
- Morris D. Ward
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable depth first-in, first-out memory
- Patent number 5,097,442
- Issue date Mar 17, 1992
- Texas Instruments Incorporated
- M. Dwayne Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable status flag generator FIFO using gray code
- Patent number 5,084,841
- Issue date Jan 28, 1992
- Texas Instruments Incorporated
- Kenneth L. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First-in, first-out memory with counter address pointers for genera...
- Patent number 4,864,543
- Issue date Sep 5, 1989
- Texas Instruments Incorporated
- Morris D. Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascadable first-in, first-out memory
- Patent number 4,839,866
- Issue date Jun 13, 1989
- Texas Instruments Incorporated
- Morris D. Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for simultaneous address increment and memory...
- Patent number 4,829,475
- Issue date May 9, 1989
- Texas Instruments Incorporated
- Morris D. Ward
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO DECODE DUAL-TONE SIGNALS
- Publication number 20100008493
- Publication date Jan 14, 2010
- Steven Edward Marum
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND CIRCUIT FOR CONTROLLING OPERATION OF A LIGHT-EMITTING DIODE
- Publication number 20080116827
- Publication date May 22, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Kenneth L. Williams
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Linking addressable shadow port and protocol for serial bus networks
- Publication number 20070067519
- Publication date Mar 22, 2007
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Linking addressable shadow port and protocol for serial bus networks
- Publication number 20050289267
- Publication date Dec 29, 2005
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Linking addressable shadow port and protocol for serial bus networks
- Publication number 20040037303
- Publication date Feb 26, 2004
- Rakesh N. Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous FIFO memory having built-in self test logic
- Publication number 20030107937
- Publication date Jun 12, 2003
- Kenneth L. Williams
- G11 - INFORMATION STORAGE

Kenneth L. Williams

Person

Patents Grantslast 30 patents

Methods and apparatus to decode dual-tone signals

Method and circuit for controlling operation of a light-emitting diode

Linking addressable shadow port and protocol for serial bus networks

Linking addressable shadow port and protocol for serial bus networks

Linking addressable shadow port and protocol for serial bus networks

Asynchronous FIFO memory having built-in self test logic

Fast FiFo memory storage system

Fast reprogrammable FIFO status flags system

Direct memory access controller with split channel transfer capabil...

DMA controller with split channel transfer capability and FIFO buff...

Sequential memory

Fifo with fast retransmit mode

First-in first-out memory

Sequential memory

Programmable depth first-in, first-out memory

Programmable status flag generator FIFO using gray code

First-in, first-out memory with counter address pointers for genera...

Cascadable first-in, first-out memory

Method and apparatus for simultaneous address increment and memory...

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO DECODE DUAL-TONE SIGNALS

METHOD AND CIRCUIT FOR CONTROLLING OPERATION OF A LIGHT-EMITTING DIODE

Linking addressable shadow port and protocol for serial bus networks

Linking addressable shadow port and protocol for serial bus networks

Linking addressable shadow port and protocol for serial bus networks

Asynchronous FIFO memory having built-in self test logic