Kenneth P. Fuchs

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Analog capacitor in dual damascene process
- Patent number 7,176,082
- Issue date Feb 13, 2007
- LSI Logic Corporation
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a metal-insulator-metal capacitor in an interconn...
- Patent number 7,118,985
- Issue date Oct 10, 2006
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Analog capacitor in dual damascene process
- Patent number 6,822,282
- Issue date Nov 23, 2004
- LSI Logic Corporation
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming analog capacitor dual damascene process
- Patent number 6,596,579
- Issue date Jul 22, 2003
- LSI Logic Corporation
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device comprising low dielectric constant materi...
- Patent number 6,522,005
- Issue date Feb 18, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant material in integrated circuit
- Patent number 6,522,006
- Issue date Feb 18, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,504,249
- Issue date Jan 7, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,504,250
- Issue date Jan 7, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect-embedded metal-insulator-metal capacitor
- Patent number 6,504,202
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for using low dielectric constant material in integrated cir...
- Patent number 6,448,653
- Issue date Sep 10, 2002
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of electrically connecting and isolating components with ver...
- Patent number 6,358,837
- Issue date Mar 19, 2002
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,208,029
- Issue date Mar 27, 2001
- Hyundai Electronics America
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation method utilizing a high pressure oxidation
- Patent number 6,071,817
- Issue date Jun 6, 2000
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High aspect ratio, metal-to-metal, linear capacitor for an integrat...
- Patent number 6,057,571
- Issue date May 2, 2000
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Global planarization using SOG and CMP
- Patent number 6,010,963
- Issue date Jan 4, 2000
- Hyundai Electronics America
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming titanium silicide local interconnect
- Patent number 5,543,361
- Issue date Aug 6, 1996
- AT&T Global Information Solutions Company
- Steven S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an amorphous silicon programmable element
- Patent number 5,447,880
- Issue date Sep 5, 1995
- AT&T Global Information Solutions Company
- Steven S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming titanium silicide local interconnect
- Patent number 5,443,996
- Issue date Aug 22, 1995
- AT&T Global Information Solutions Company
- Steven S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for using low dielectric constant material in integrated cir...
- Patent number 5,438,022
- Issue date Aug 1, 1995
- AT&T Global Information Solutions Company
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Global planarization using SOG and CMP
- Patent number 5,312,512
- Issue date May 17, 1994
- NCR Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Analog capacitor in dual damascene process
- Publication number 20050042818
- Publication date Feb 24, 2005
- LSI Logic Corporation
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Analog capacitor in dual damascene process
- Publication number 20030176035
- Publication date Sep 18, 2003
- LSI Logic Corporation
- Todd A. Randazzo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit fabrication dual plasma process with separate in...
- Publication number 20030068858
- Publication date Apr 10, 2003
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS

Kenneth P. Fuchs

Person

Patents Grantslast 30 patents

Analog capacitor in dual damascene process

Method of forming a metal-insulator-metal capacitor in an interconn...

Analog capacitor in dual damascene process

Method of forming analog capacitor dual damascene process

Integrated circuit device comprising low dielectric constant materi...

Low dielectric constant material in integrated circuit

Integrated circuit device with reduced cross talk

Integrated circuit device with reduced cross talk

Interconnect-embedded metal-insulator-metal capacitor

Method for using low dielectric constant material in integrated cir...

Method of electrically connecting and isolating components with ver...

Integrated circuit device with reduced cross talk

Isolation method utilizing a high pressure oxidation

High aspect ratio, metal-to-metal, linear capacitor for an integrat...

Global planarization using SOG and CMP

Process for forming titanium silicide local interconnect

Method for forming an amorphous silicon programmable element

Process for forming titanium silicide local interconnect

Method for using low dielectric constant material in integrated cir...

Global planarization using SOG and CMP

Patents Applicationslast 30 patents

Analog capacitor in dual damascene process

Analog capacitor in dual damascene process

Integrated circuit fabrication dual plasma process with separate in...