Kevin X. Zhang

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of forming secured metal gate antifuse structures
- Patent number 9,123,724
- Issue date Sep 1, 2015
- Intel Corporation
- Xianghong Tong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM with pulse sense amp
- Patent number 9,013,941
- Issue date Apr 21, 2015
- Intel Corporation
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline floating during non-access mode for memory arrays
- Patent number 8,982,659
- Issue date Mar 17, 2015
- Intel Corporation
- Tsung-Yung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of forming secured metal gate antifuse structures
- Patent number 8,618,613
- Issue date Dec 31, 2013
- Intel Corporation
- Xianghong Tong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
6F2 DRAM cell
- Patent number 8,519,462
- Issue date Aug 27, 2013
- Intel Corporation
- Yih Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive and dynamic stability enhancement for memories
- Patent number 8,451,670
- Issue date May 28, 2013
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable read only memory
- Patent number 8,411,482
- Issue date Apr 2, 2013
- Intel Corporation
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical DRAM sensing
- Patent number 8,406,073
- Issue date Mar 26, 2013
- Intel Corporation
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Grant
Antifuse programmable memory array
- Patent number 8,395,923
- Issue date Mar 12, 2013
- Intel Corporation
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Tamper resistant fuse design
- Patent number 8,242,831
- Issue date Aug 14, 2012
- Intel Corporation
- Xianghong Tong
- G11 - INFORMATION STORAGE
Information Patent Grant
Common plate capacitor array connections, and processes of making same
- Patent number 7,981,756
- Issue date Jul 19, 2011
- Intel Corporation
- Nick Lindert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Area efficient programmable read only memory (PROM) array
- Patent number 7,924,596
- Issue date Apr 12, 2011
- Intel Corporation
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache leakage shut-off mechanism
- Patent number 7,657,767
- Issue date Feb 2, 2010
- Intel Corporation
- Stefan Rusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fuse cell array with redundancy features
- Patent number 7,602,663
- Issue date Oct 13, 2009
- Intel Corporation
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Fuse cell having adjustable sensing margin
- Patent number 7,417,913
- Issue date Aug 26, 2008
- Intel Corporation
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with dynamically adjustable supply
- Patent number 7,403,426
- Issue date Jul 22, 2008
- Intel Corporation
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting multi-hit errors in a cache
- Patent number 7,337,372
- Issue date Feb 26, 2008
- Intel Corporation
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell having p-type pass device
- Patent number 7,230,842
- Issue date Jun 12, 2007
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
Six-transistor (6T) static random access memory (SRAM) with dynamic...
- Patent number 7,177,176
- Issue date Feb 13, 2007
- Intel Corporation
- Bo Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared cache wordline decoder for redundant and regular addresses
- Patent number 7,089,360
- Issue date Aug 8, 2006
- Intel Corporation
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic multi-Vcc scheme for SRAM cell stability control
- Patent number 7,079,426
- Issue date Jul 18, 2006
- Intel Corporation
- Kevin Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic voltage scaling scheme for an on-die voltage differentiator...
- Patent number 6,992,405
- Issue date Jan 31, 2006
- Intel Corporation
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-down scheme for an on-die voltage differentiator design
- Patent number 6,982,500
- Issue date Jan 3, 2006
- Intel Corporation
- Kevin X. Zhang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for providing supply voltages for a processor
- Patent number 6,948,079
- Issue date Sep 20, 2005
- Intel Corporation
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory
- Patent number 6,862,207
- Issue date Mar 1, 2005
- Intel Corporation
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer for a split cache line access
- Patent number 6,862,225
- Issue date Mar 1, 2005
- Intel Corporation
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Communication bus for low voltage swing data signals
- Patent number 6,816,554
- Issue date Nov 9, 2004
- Intel Corporation
- Kevin X. Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Buffer for a split cache line access
- Patent number 6,778,444
- Issue date Aug 17, 2004
- Intel Corporation
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing technique for a high density SRAM
- Patent number 6,775,181
- Issue date Aug 10, 2004
- Intel Corporation
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Tag design for cache access with redundant-form address
- Patent number 6,707,752
- Issue date Mar 16, 2004
- Intel Corporation
- Kevin Zhang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DRAM WITH PULSED SENSE AMP
- Publication number 20140269009
- Publication date Sep 18, 2014
- Swaroop Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURES
- Publication number 20140103448
- Publication date Apr 17, 2014
- Xianghong Tong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
6F2 DRAM Cell
- Publication number 20120326218
- Publication date Dec 27, 2012
- Yih Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURES
- Publication number 20120248546
- Publication date Oct 4, 2012
- Xianghong Tong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adaptive and Dynamic Stability Enhancement for Memories
- Publication number 20120075938
- Publication date Mar 29, 2012
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
TAMPER RESISTANT FUSE DESIGN
- Publication number 20110156801
- Publication date Jun 30, 2011
- Xianghong Tong
- G11 - INFORMATION STORAGE
Information Patent Application
BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS
- Publication number 20110149666
- Publication date Jun 23, 2011
- Tsung-Yung Chang
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED AREA MEMORY ARRAY BY USING SENSE AMPLIFIER AS WRITE DRIVER
- Publication number 20110149667
- Publication date Jun 23, 2011
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE
Information Patent Application
ANTIFUSE PROGRAMMABLE MEMORY ARRAY
- Publication number 20100165699
- Publication date Jul 1, 2010
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Common plate capacitor array connections, and processes of making same
- Publication number 20100155887
- Publication date Jun 24, 2010
- Nick Lindert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable read only memory
- Publication number 20100046269
- Publication date Feb 25, 2010
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT PROGRAMMABLE READ ONLY MEMORY (PROM) ARRAY
- Publication number 20090080232
- Publication date Mar 26, 2009
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Fuse cell array with redundancy features
- Publication number 20080151593
- Publication date Jun 26, 2008
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Shared sense amplifier for fuse cell
- Publication number 20070217247
- Publication date Sep 20, 2007
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Fuse cell having adjustable sensing margin
- Publication number 20070217251
- Publication date Sep 20, 2007
- Zhanping Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic body bias with bias boost
- Publication number 20070153610
- Publication date Jul 5, 2007
- Intel Corporation
- Fatih Hamzaoglu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory cell having p-type pass device
- Publication number 20070058419
- Publication date Mar 15, 2007
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
Cache leakage shut-off mechanism
- Publication number 20070005999
- Publication date Jan 4, 2007
- Stefan Rusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory with dynamically adjustable supply
- Publication number 20060268626
- Publication date Nov 30, 2006
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic multi-Vcc scheme for SRAM cell stability control
- Publication number 20060067134
- Publication date Mar 30, 2006
- Kevin Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Six-transistor (6T) static random access memory (SRAM) with dynamic...
- Publication number 20060002177
- Publication date Jan 5, 2006
- Bo Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
Static random access memory
- Publication number 20050157537
- Publication date Jul 21, 2005
- Intel Corporation
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Application
NOVEL BUFFER FOR A SPLIT CACHE LINE ACCESS
- Publication number 20040260878
- Publication date Dec 23, 2004
- Intel Corporation
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Biasing technique for a high density SRAM
- Publication number 20040095811
- Publication date May 20, 2004
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Static random access memory
- Publication number 20040071010
- Publication date Apr 15, 2004
- Liqiong Wei
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for detecting multi-hit errors in a cache
- Publication number 20040049713
- Publication date Mar 11, 2004
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic voltage scaling scheme for an on-die voltage differentiator...
- Publication number 20030168915
- Publication date Sep 11, 2003
- Kevin X. Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Power-down scheme for an on-die voltage differentiator design
- Publication number 20030168914
- Publication date Sep 11, 2003
- Kevin X. Zhang
- G05 - CONTROLLING REGULATING
Information Patent Application
Method and apparatus for providing multiple supply voltages for a p...
- Publication number 20030122429
- Publication date Jul 3, 2003
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling a supply voltage to a processor
- Publication number 20030126477
- Publication date Jul 3, 2003
- Kevin X. Zhang
- G06 - COMPUTING CALCULATING COUNTING

Kevin X. Zhang

Person

Patents Grantslast 30 patents

Methods of forming secured metal gate antifuse structures

DRAM with pulse sense amp

Bitline floating during non-access mode for memory arrays

Methods of forming secured metal gate antifuse structures

6F2 DRAM cell

Adaptive and dynamic stability enhancement for memories

Programmable read only memory

Hierarchical DRAM sensing

Antifuse programmable memory array

Tamper resistant fuse design

Common plate capacitor array connections, and processes of making same

Area efficient programmable read only memory (PROM) array

Cache leakage shut-off mechanism

Fuse cell array with redundancy features

Fuse cell having adjustable sensing margin

Memory with dynamically adjustable supply

Method and apparatus for detecting multi-hit errors in a cache

Memory cell having p-type pass device

Six-transistor (6T) static random access memory (SRAM) with dynamic...

Shared cache wordline decoder for redundant and regular addresses

Dynamic multi-Vcc scheme for SRAM cell stability control

Dynamic voltage scaling scheme for an on-die voltage differentiator...

Power-down scheme for an on-die voltage differentiator design

Method and apparatus for providing supply voltages for a processor

Static random access memory

Buffer for a split cache line access

Communication bus for low voltage swing data signals

Buffer for a split cache line access

Biasing technique for a high density SRAM

Tag design for cache access with redundant-form address

Patents Applicationslast 30 patents

DRAM WITH PULSED SENSE AMP

METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURES

6F2 DRAM Cell

METHODS OF FORMING SECURED METAL GATE ANTIFUSE STRUCTURES

Adaptive and Dynamic Stability Enhancement for Memories

TAMPER RESISTANT FUSE DESIGN

BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS

REDUCED AREA MEMORY ARRAY BY USING SENSE AMPLIFIER AS WRITE DRIVER

ANTIFUSE PROGRAMMABLE MEMORY ARRAY

Common plate capacitor array connections, and processes of making same

Programmable read only memory

AREA EFFICIENT PROGRAMMABLE READ ONLY MEMORY (PROM) ARRAY

Fuse cell array with redundancy features

Shared sense amplifier for fuse cell

Fuse cell having adjustable sensing margin

Dynamic body bias with bias boost

Memory cell having p-type pass device

Cache leakage shut-off mechanism

Memory with dynamically adjustable supply

Dynamic multi-Vcc scheme for SRAM cell stability control

Six-transistor (6T) static random access memory (SRAM) with dynamic...

Static random access memory

NOVEL BUFFER FOR A SPLIT CACHE LINE ACCESS

Biasing technique for a high density SRAM

Static random access memory

Method and apparatus for detecting multi-hit errors in a cache

Dynamic voltage scaling scheme for an on-die voltage differentiator...

Power-down scheme for an on-die voltage differentiator design

Method and apparatus for providing multiple supply voltages for a p...

Method and apparatus for controlling a supply voltage to a processor