Khalid Sirajuddin

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Edge ring for bevel polymer reduction
- Patent number 10,903,055
- Issue date Jan 26, 2021
- Applied Materials, Inc.
- Rohit Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post etch reactive plasma milling to smooth through substrate via s...
- Patent number 9,039,908
- Issue date May 26, 2015
- Applied Materials, Inc.
- Jon Farr
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Increased deposition efficiency and higher chamber conductance with...
- Patent number 9,023,227
- Issue date May 5, 2015
- Applied Materials, Inc.
- Jivko Dinev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for etching through-silicon vias with tunable profile angles
- Patent number 8,987,140
- Issue date Mar 24, 2015
- Applied Materials, Inc.
- Puneet Bajaj
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a deep trench in a substrate
- Patent number 8,158,522
- Issue date Apr 17, 2012
- Applied Materials, Inc.
- Khalid M. Sirajuddin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
EDGE RING FOR BEVEL POLYMER REDUCTION
- Publication number 20160307742
- Publication date Oct 20, 2016
- Applied Materials, Inc.
- Rohit MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ETCHING A SUBSTRATE
- Publication number 20140335679
- Publication date Nov 13, 2014
- TONG LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR PERFORMING A VIA REVEAL ETCHING PROCESS FOR FORMING THR...
- Publication number 20140199833
- Publication date Jul 17, 2014
- Applied Materials, Inc.
- Rohit MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Edge Protection and Efficiency Using Inert Gas and Ring
- Publication number 20140179108
- Publication date Jun 26, 2014
- Dung Huu Le
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING DUAL DAMASCENE INTERCONNECT STRUCTURES
- Publication number 20130288474
- Publication date Oct 31, 2013
- Applied Materials, Inc.
- ROHIT MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INCREASED DEPOSITION EFFICIENCY AND HIGHER CHAMBER CONDUCTANCE WITH...
- Publication number 20130005152
- Publication date Jan 3, 2013
- Applied Materials, Inc.
- JIVKO DINEV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES
- Publication number 20120270404
- Publication date Oct 25, 2012
- Applied Materials, Inc.
- Puneet Bajaj
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FILLING A DEEP TRENCH IN A SUBSTRATE
- Publication number 20110217832
- Publication date Sep 8, 2011
- Digvijay Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A DEEP TRENCH IN A SUBSTRATE
- Publication number 20110201205
- Publication date Aug 18, 2011
- Khalid M. Sirajuddin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Post etch reactive plasma milling to smooth through substrate via s...
- Publication number 20100055400
- Publication date Mar 4, 2010
- APPLIED MATERIALS, INC.
- Jon Farr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS OF A SUBSTRATE ETCHING SYSTEM AND PROCESS
- Publication number 20090272717
- Publication date Nov 5, 2009
- Applied Materials, Inc.
- Sharma V. Pamarthy
- H01 - BASIC ELECTRIC ELEMENTS

Khalid Sirajuddin

Person

Patents Grantslast 30 patents

Edge ring for bevel polymer reduction

Post etch reactive plasma milling to smooth through substrate via s...

Increased deposition efficiency and higher chamber conductance with...

Methods for etching through-silicon vias with tunable profile angles

Method of forming a deep trench in a substrate

Patents Applicationslast 30 patents

EDGE RING FOR BEVEL POLYMER REDUCTION

METHODS FOR ETCHING A SUBSTRATE

METHODS FOR PERFORMING A VIA REVEAL ETCHING PROCESS FOR FORMING THR...

Wafer Edge Protection and Efficiency Using Inert Gas and Ring

METHODS FOR FABRICATING DUAL DAMASCENE INTERCONNECT STRUCTURES

INCREASED DEPOSITION EFFICIENCY AND HIGHER CHAMBER CONDUCTANCE WITH...

METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES

METHOD OF FILLING A DEEP TRENCH IN A SUBSTRATE

METHOD OF FORMING A DEEP TRENCH IN A SUBSTRATE

Post etch reactive plasma milling to smooth through substrate via s...

METHOD AND APPARATUS OF A SUBSTRATE ETCHING SYSTEM AND PROCESS