1) Field
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of filling deep trenches in substrates.
2) Description of Related Art
Conventional deposition processes of liner dielectric layers in deep trenches, such as deep silicon via trenches, often exhibit some level of shoulder formation in the deposition profile. During subsequent metal deposition processes, such shoulders in the dielectric liner can inhibit complete filling of a deep trench by conductive layers. Void formation may result.
Embodiments of the present invention include methods of filling deep trenches in substrates.
In an embodiment, a method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process.
In another embodiment, a method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing all of the dielectric layer at the bottom of the deep trench with a relatively high bias plasma etch process. In accordance with an embodiment of the present invention, such an opening of a bottom oxide is useful in a post through silicon via integration process flow.
Methods of filling deep trenches in substrates are described. In the following description, numerous specific details are set forth, such as deposition and etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as photolithography patterning and development techniques for trench formation, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
Disclosed herein are methods of filling deep trenches in substrates. In an embodiment, a method includes providing a substrate with a deep trench formed therein. A dielectric layer is then formed conformal with the substrate and the deep trench. Then, with the entire portion of the dielectric layer conformal with the deep trench exposed, at least a portion, but not all, of the dielectric layer at the top of the deep trench is removed with a relatively low bias plasma etch process. In another embodiment, a method includes providing a substrate with a deep trench formed therein. A dielectric layer is then formed conformal with the substrate and the deep trench. Then, with the entire portion of the dielectric layer conformal with the deep trench exposed, all of the dielectric layer at the bottom of the deep trench is removed with a relatively high bias plasma etch process.
The bias of an etch process may be manipulated to locate a primary etch pathway at a particular location on a film. For example, in accordance with an embodiment of the present invention, the shoulders of a dielectric layer in a deep trench are reduced or removed with a relatively low bias etch process to enable improved filling of the deep trench with subsequently deposited layers. In that embodiment, the relatively low bias targets etching of the dielectric layer at the top portion of the deep trench without significantly etching the dielectric layer deeper into the deep trench. In accordance with another embodiment of the present invention, the portion of a dielectric layer at the bottom of a deep trench is removed with a relatively high bias etch process to enable formation of desired features of the deep trench. In that embodiment, the relatively high bias targets etching of the dielectric layer at the bottom portion of the deep trench without significantly etching the dielectric layer in the upper regions of the deep trench. In particular embodiments, a deep trench is a trench having a depth approximately in the range of 1 micron to several hundred microns. In particular embodiments, the terms “filled” or “filling” without further clarification can mean “partially filled” or “partially filling,” “mostly filled” or “mostly filling,” essentially filled” or essentially filling,” or “completely filled” or “completely filling.”
A deep trench etch may be filled using conventional deposition processes. As an example,
Referring to
Referring to
Referring to
In an aspect of the present invention, the shoulders of a dielectric layer in a deep trench are reduced or removed with a relatively low bias etch process to enable improved filling of the deep trench with subsequently deposited layers. For example,
Referring to operation 202 of Flowchart 200 and corresponding
Substrate 300 may be composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably reside. In accordance with an embodiment of the present invention, substrate 300 is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing substrate 300 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, substrate 300 is composed of a III-V material.
Deep trench 302 may be formed by a process suitable to form a deep trench having approximately the same dimensions, e.g. width, at the top of the trench as the bottom of the trench. In accordance with an embodiment of the present invention, deep trench 302 is formed by first forming a patterning film formed above substrate 300 and then etching substrate 300. The patterning film may be composed of a material suitable for deposition and patterning on a substrate. In an embodiment, the patterning film is composed of a layer of photo-resist and is suitable to withstand a deep substrate etch. The photo-resist layer may be composed of a material suitable for use in a lithographic process. In an embodiment, the photo-resist layer is exposed to a light source and subsequently developed. In one embodiment, the portions of the photo-resist layer to be exposed to the light source will be removed upon developing the photo-resist layer, e.g., the photo-resist layer is composed of a positive photo-resist material. In a specific embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultra-violet (EUV) resist and a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the portions of the photo-resist layer to be exposed to the light source will be retained upon developing the photo-resist layer, e.g., the photo-resist layer is composed of a negative photo-resist material. In a specific embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate. In an embodiment, the patterning film is composed of an I-line or G-line photo-resist material layer. In an embodiment, upon patterning the patterning film, substrate 300 is etched, e.g. by a plasma etch, in the regions of substrate 300 exposed by the pattern of the patterning film. In accordance with an embodiment of the present invention, deep trench 302 has scalloped features, as described in association with
Referring to operation 204 of Flowchart 200 and corresponding
Dielectric layer 304 may be a material layer suitable for use as an insulating layer. In accordance with an embodiment of the present invention, the insulating layer is composed of a material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, silicon oxy-nitride or a high-k dielectric layer. In a particular embodiment, forming dielectric layer 304 includes forming a layer consisting essentially of silicon dioxide. In an embodiment, dielectric layer 304 has a thickness approximately in the range of sub-100 nanometer-3 microns.
Referring to operation 206 of Flowchart 200 and corresponding
The low bias etch process may be an etch process suitable to mostly etch, or even entirely etch, dielectric layer 304 at a location near or at the top of deep trench 306 without significantly etching other regions of dielectric layer 304. In accordance with an embodiment of the present invention, removing the portion of dielectric layer 304 with the relatively low bias plasma etch process includes applying a bias approximately in the range of 0-200 Watts. In one embodiment, removing the portion of dielectric layer 304 with the relatively low bias plasma etch process includes applying a bias approximately in the range of 0-100 Watts. In a specific embodiment, removing the portion of dielectric layer 304 with the relatively low bias plasma etch process includes using a gaseous composition such as, but not limited to, helium or argon carrier gas approximately in the range of 0-400 sccm, along with a gas such as, but not limited to, SF6 gas approximately in the range of 0-500 sccm, C4F8 gas approximately in the range of 0-500 sccm, CHF3 gas approximately in the range of 0-500 sccm, CF4 gas approximately in the range of 0-500 sccm, or O2 gas approximately in the range of 0-100 sccm, the gaseous composition having a pressure approximately in the range of 10-200 mTorr, and the gaseous composition having a source power applied thereto approximately in the range of 1000-5000 Watts.
Referring to
Barrier layer 314 may be composed of a material suitable to inhibit electro-migration within metal interconnects, to prevent oxidation of the metal interconnects, or to provide a surface for nucleation in a damascene process. In accordance with an embodiment of the present invention, barrier layer 314 is composed of a material such as, but not limited to, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. In an embodiment, the thickness of barrier layer 314 is approximately in the range of 5-15 nanometers.
Seed layer 316 may be composed of a material suitable to provide a surface for nucleation in a damascene process. In accordance with an embodiment of the present invention, seed layer 316 is composed of a material such as, but not limited to, copper or a copper/aluminum alloy.
Referring to
Metal fill layer 320 may be composed of a suitable material that can conduct a current from one end of a metal interconnect to another end of the metal interconnect. In accordance with an embodiment of the present invention, metal fill layer 320 is composed of a material such as, but not limited to, copper, silver, aluminum or an alloy thereof.
In another aspect of the present invention, the portion of a dielectric layer at the bottom of a deep trench is removed with a relatively high bias etch process to enable formation of desired features of the deep trench, such as formation of contacts absent a dielectric cap at the bottom of a deep trench. For example,
Referring to operation 402 of Flowchart 400 and corresponding
Substrate 500 may be composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably reside. In accordance with an embodiment of the present invention, substrate 500 is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing substrate 500 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, substrate 500 is composed of a III-V material.
Deep trench 502 may be formed by a process suitable to form a deep trench having approximately the same dimensions, e.g. width, at the top of the trench as the bottom of the trench. In accordance with an embodiment of the present invention, deep trench 502 is formed by first forming a patterning film formed above substrate 500 and then etching substrate 500. The patterning film may be composed of a material suitable for deposition and patterning on a substrate. In an embodiment, the patterning film is composed of a layer of photo-resist and is suitable to withstand a deep substrate etch. The photo-resist layer may be composed of a material suitable for use in a lithographic process. In an embodiment, the photo-resist layer is exposed to a light source and subsequently developed. In one embodiment, the portions of the photo-resist layer to be exposed to the light source will be removed upon developing the photo-resist layer, e.g., the photo-resist layer is composed of a positive photo-resist material. In a specific embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultra-violet (EUV) resist and a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the portions of the photo-resist layer to be exposed to the light source will be retained upon developing the photo-resist layer, e.g., the photo-resist layer is composed of a negative photo-resist material. In a specific embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate. In an embodiment, the patterning film is composed of an I-line or G-line photo-resist material layer. In an embodiment, upon patterning the patterning film, substrate 500 is etched, e.g. by a plasma etch, in the regions of substrate 500 exposed by the pattern of the patterning film.
Referring to operation 404 of Flowchart 400 and corresponding
Dielectric layer 504 may be a material layer suitable for use as an insulating layer. In accordance with an embodiment of the present invention, the insulating layer is composed of a material such as, but not limited to, silicon oxide, silicon dioxide, silicon nitride, silicon oxy-nitride or a high-k dielectric layer. In a particular embodiment, forming dielectric layer 504 includes forming a layer consisting essentially of silicon dioxide. In an embodiment, dielectric layer 304 has a thickness approximately in the range of sub-100 nanometer-3 microns.
Referring to operation 406 of Flowchart 400 and corresponding
The high bias etch process may be an etch process suitable to entirely remove the portion of dielectric layer 504 at the bottom of deep trench 502 without significantly etching other regions of dielectric layer 504, such as without etching portions of dielectric layer 504 at the top of deep trench 502. However, in an embodiment, as described above, shoulders 508 are formed during the formation of dielectric layer 504. In one embodiment, shoulders 508 allow some residual etching of the portions of dielectric layer 504 at the top of deep trench 502, during removal of the portion of dielectric layer 504 at the bottom of deep trench 502, without significant detrimental impact to the final structure. In an alternative embodiment, shoulders 508 are not formed during the formation of dielectric layer 504 and are therefore not present for removal during the etching of the portion of dielectric layer 504 at the bottom of deep trench 502. In another alternative embodiment, the trench width to shoulder size ratio is large and the impact of the shoulders on the process is minimal. In another alternative embodiment, the trench width to dielectric layer 504 thickness ratio is large and the impact of the shoulders on the process is minimal.
In accordance with an embodiment of the present invention, removing the portion of dielectric layer 504 at the bottom of deep trench 502 with the relatively high bias plasma etch process includes applying a bias approximately in the range of 100-1000 Watts. In one embodiment, removing the portion of dielectric layer 504 at the bottom of deep trench 502 with the relatively high bias plasma etch process includes applying a bias approximately in the range of 300-500 Watts. In a specific embodiment, removing the portion of dielectric layer 504 at the bottom of deep trench 502 with the relatively high bias plasma etch process includes using a gaseous composition such as, but not limited to, helium or argon carrier gas approximately in the range of 0-400 sccm, along with a gas such as, but not limited to, SF6 gas approximately in the range of 0-500 sccm, C4F8 gas approximately in the range of 0-500 sccm, CHF3 gas approximately in the range of 0-500 sccm, CF4 gas approximately in the range of 0-500 sccm, or O2 gas approximately in the range of 0-100 sccm, the gaseous composition having a pressure approximately in the range of 10-200 mTorr, and the gaseous composition having a source power applied thereto approximately in the range of 1000-5000 Watts.
Although not depicted, the method of filling a deep trench in a substrate may also include forming a barrier layer and a seed layer on modified dielectric layer 505 and in deep trench 502 to form a partially filled trench. In accordance with an embodiment of the present invention, the barrier layer and the seed layer are formed at the bottom of the deep trench, where the portion of dielectric layer 504 has been removed.
The barrier layer may be composed of a material suitable to inhibit electro-migration within metal interconnects, to prevent oxidation of the metal interconnects, or to provide a surface for nucleation in a damascene process. In accordance with an embodiment of the present invention, the barrier layer is composed of a material such as, but not limited to, tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. In an embodiment, the thickness of the barrier layer is approximately in the range of 5-15 nanometers.
The seed layer may be composed of a material suitable to provide a surface for nucleation in a damascene process. In accordance with an embodiment of the present invention, the seed layer is composed of a material such as, but not limited to, copper or a copper/aluminum alloy.
Although also not depicted, the method of filling a deep trench in a substrate may also include forming a metal fill layer on the seed layer and in the partially filled trench to form an essentially or completely filled trench. In accordance with an embodiment of the present invention, the metal fill layer is composed of a material such as, but not limited to, copper, silver, aluminum or an alloy thereof. In an embodiment, modified dielectric layer 505, the barrier layer, the seed layer, and the metal fill layer essentially fill the deep trench. In a specific embodiment, modified dielectric layer 505, the barrier layer, the seed layer, and the metal fill layer essentially fill the deep trench.
In another aspect of the present invention, a repeated etch/substrate sidewall deposition cycle process may preliminarily be included for trench formation in a process wherein the portion of a dielectric layer at the bottom of a deep trench is removed with a relatively high bias etch process. In such an approach, a repeated etch/substrate sidewall deposition cycle process is applied, wherein a material layer is iteratively formed on the sidewalls of the deep trench throughout its formation. This approach may lead to the formation of scalloped features on the sidewalls of a deep trench, as described below.
Referring to
Referring to
Referring to
The high bias etch process may be an etch process suitable to entirely remove the portion of dielectric layer 604 at the bottom of deep trench 602 without significantly etching other regions of dielectric layer 604, such as without etching portions of dielectric layer 604 at the top of deep trench 602. However, in an embodiment, as described above, shoulders 608 are formed during the formation of dielectric layer 604. In one embodiment, shoulders 608 allow some residual etching of the portions of dielectric layer 604 at the top of deep trench 602, during removal of the portion of dielectric layer 604 at the bottom of deep trench 602, without significant detrimental impact to the final structure. In an alternative embodiment, shoulders 608 are not formed during the formation of dielectric layer 604 and are therefore not present for removal during the etching of the portion of dielectric layer 604 at the bottom of deep trench 602.
In accordance with an embodiment of the present invention, removing the portion of dielectric layer 604 at the bottom of deep trench 602 with the relatively high bias plasma etch process includes applying a bias approximately in the range of 100-1000 Watts. In one embodiment, removing the portion of dielectric layer 604 at the bottom of deep trench 602 with the relatively high bias plasma etch process includes applying a bias approximately in the range of 300-500 Watts. In a specific embodiment, removing the portion of dielectric layer 604 at the bottom of deep trench 602 with the relatively high bias plasma etch process includes using a gaseous composition such as, but not limited to, helium or argon carrier gas approximately in the range of 0-400 sccm, along with a gas such as, but not limited to, SF6 gas approximately in the range of 0-500 sccm, C4F8 gas approximately in the range of 0-500 sccm, CHF3 gas approximately in the range of 0-500 sccm, CF4 gas approximately in the range of 0-500 sccm, or O2 gas approximately in the range of 0-100 sccm, the gaseous composition having a pressure approximately in the range of 10-200 mTorr, and the gaseous composition having a source power applied thereto approximately in the range of 1000-5000 Watts.
Although not depicted, the method of filling a deep trench in a substrate may also include forming a barrier layer and a seed layer on modified dielectric layer 605 and in deep trench 602 to form a partially filled trench. In accordance with an embodiment of the present invention, the barrier layer and the seed layer are formed at the bottom of the deep trench, where the portion of dielectric layer 604 has been removed. The barrier layer may be composed of a material such as the materials described in association with the barrier layer discussed above following the
Although also not depicted, the method of filling a deep trench in a substrate may also include forming a metal fill layer on the seed layer and in the partially filled trench to form an essentially or completely filled trench. In accordance with an embodiment of the present invention, the metal fill layer is composed of a material such as, but not limited to, copper, silver, aluminum or an alloy thereof. In an embodiment, modified dielectric layer 605, the barrier layer, the seed layer, and the metal fill layer essentially fill the deep trench. In a specific embodiment, modified dielectric layer 605, the barrier layer, the seed layer, and the metal fill layer essentially fill the deep trench.
Thus, methods of filling deep trenches in substrates have been disclosed. In accordance with an embodiment of the present invention, a method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process. In one embodiment, forming the dielectric layer conformal with the substrate and the deep trench includes forming a pair of shoulders at the top portion of the deep trench, and removing the portion of the dielectric layer at the top of the deep trench includes removing at least a portion of the pair of shoulders. In another embodiment, the method further includes, subsequent to removing the portion of the dielectric layer, forming a barrier layer conformal with the dielectric layer and the deep trench. A seed layer is then formed conformal with the barrier layer and the deep trench. A metal fill layer is then formed conformal with the seed layer and the deep trench. The dielectric layer, the barrier layer, the seed layer, and the metal fill layer essentially or completely fill the deep trench.
This application claims the benefit of U.S. Provisional Application No. 61/247,447, filed Sep. 30, 2009, the entire contents of which are hereby incorporated by reference herein.
Number | Date | Country | |
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61247447 | Sep 2009 | US |