Khanh Tran

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Punch-through via with conformal barrier liner
- Patent number 6,522,013
- Issue date Feb 18, 2003
- Advanced Micro Devices, Inc.
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMA...
- Patent number 6,492,258
- Issue date Dec 10, 2002
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
H2 diffusion barrier formation by nitrogen incorporation in oxide...
- Patent number 6,472,751
- Issue date Oct 29, 2002
- Advanced Micro Devices, Inc.
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer processing apparatus and method
- Patent number 6,455,098
- Issue date Sep 24, 2002
- Semix Incorporated
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-K sub spacer pocket formation for gate capacitance reduction
- Patent number 6,351,013
- Issue date Feb 26, 2002
- Advanced Micro Devices, Inc.
- Scott Luning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing stress-induced voids for 0.25mμ and smal...
- Patent number 6,329,718
- Issue date Dec 11, 2001
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias with HSQ gap filled metal patterns having high etch...
- Patent number 6,319,859
- Issue date Nov 20, 2001
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias
- Patent number 6,232,221
- Issue date May 15, 2001
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High integrity borderless vias with protective sidewall spacer
- Patent number 6,232,223
- Issue date May 15, 2001
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
H2 diffusion barrier formation by nitrogen incorporation in oxide l...
- Patent number 6,194,328
- Issue date Feb 27, 2001
- Advanced Micro Devices, Inc.
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lower metal feature profile with overhanging ARC layer to improve r...
- Patent number 6,133,142
- Issue date Oct 17, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromigration resistant patterned metal layer gap filled with HSQ
- Patent number 6,100,179
- Issue date Aug 8, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High integrity vias
- Patent number 6,097,090
- Issue date Aug 1, 2000
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High integrity borderless vias with HSQ gap filled patterned conduc...
- Patent number 6,093,635
- Issue date Jul 25, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HSQ with high plasma etching resistance surface for borderless vias
- Patent number 6,087,724
- Issue date Jul 11, 2000
- Advanced Micro Devices, Inc.
- Jeffrey A. Shields
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HSQ with high plasma etching resistance surface for borderless vias
- Patent number 6,083,851
- Issue date Jul 4, 2000
- Advanced Micro Devices, Inc.
- Jeffrey A. Shields
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias with HSQ gap filled patterned metal layers
- Patent number 6,060,384
- Issue date May 9, 2000
- Advanced Micro Devices, Inc.
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density plasma oxide gap filled patterned metal layers with im...
- Patent number 6,046,106
- Issue date Apr 4, 2000
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of prevention of degradation of low dielectric constant gap-...
- Patent number 6,043,147
- Issue date Mar 28, 2000
- Advanced Micro Devices, Inc.
- Robert C. Chen
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Electromigration resistant patterned metal layer gap filled with HSQ
- Patent number 6,034,420
- Issue date Mar 7, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vacuum baked HSQ gap fill layer for high integrity borderless vias
- Patent number 6,030,891
- Issue date Feb 29, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective etching for improved dielectric interlayer planarization
- Patent number 6,008,116
- Issue date Dec 28, 1999
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced cracking in gap filling dielectrics
- Patent number 5,990,558
- Issue date Nov 23, 1999
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High integrity borderless vias with protective sidewall spacer
- Patent number 5,982,035
- Issue date Nov 9, 1999
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tapered isolated metal profile to reduce dielectric layer cracking
- Patent number 5,973,387
- Issue date Oct 26, 1999
- Advanced Micro Devices, Inc.
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias with HSQ gap filled metal patterns having high etch...
- Patent number 5,942,801
- Issue date Aug 24, 1999
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias
- Patent number 5,925,932
- Issue date Jul 20, 1999
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HSQ baking for reduced dielectric constant
- Patent number 5,888,898
- Issue date Mar 30, 1999
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HSQ processing for reduced dielectric constant
- Patent number 5,888,911
- Issue date Mar 30, 1999
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias with HSQ gap filled patterned metal layers
- Patent number 5,866,945
- Issue date Feb 2, 1999
- Advanced Micro Devices
- Robert C. Chen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LASER PATTERNED SOLID-STATE BATTERIES, AND METHODS OF MAKING AND US...
- Publication number 20240379932
- Publication date Nov 14, 2024
- Ensurge Micropower ASA
- Khanh TRAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CYLINDRICAL SOLID-STATE BATTERY, AND METHODS OF MAKING AND USING TH...
- Publication number 20240113341
- Publication date Apr 4, 2024
- Ensurge Micropower ASA
- Richard VAN DER LINDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH ENERGY-DENSITY SOLID-STATE BATTERY, AND METHOD(S) OF MAKING TH...
- Publication number 20230420731
- Publication date Dec 28, 2023
- Ensurge Micropower ASA
- Khanh TRAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PASSIVATION/ENCAPSULATION LAYER, VIA AND DISTRIBUTION LAYER, SOLID-...
- Publication number 20230378606
- Publication date Nov 23, 2023
- Ensurge Micropower ASA
- Khanh TRAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer processing apparatus and method
- Publication number 20020164849
- Publication date Nov 7, 2002
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25U AND SMALLER SEMI...
- Publication number 20020003306
- Publication date Jan 10, 2002
- MINH VAN NGO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer processing apparatus and method
- Publication number 20010055823
- Publication date Dec 27, 2001
- Semix Incorporated
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Punch-through via with conformal barrier liner

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&#x03BC;M AND SMA...

H2 diffusion barrier formation by nitrogen incorporation in oxide...

Wafer processing apparatus and method

Low-K sub spacer pocket formation for gate capacitance reduction

Method for reducing stress-induced voids for 0.25m&#x03BC; and smal...

Borderless vias with HSQ gap filled metal patterns having high etch...

Borderless vias

High integrity borderless vias with protective sidewall spacer

H2 diffusion barrier formation by nitrogen incorporation in oxide l...

Lower metal feature profile with overhanging ARC layer to improve r...

Electromigration resistant patterned metal layer gap filled with HSQ

High integrity vias

High integrity borderless vias with HSQ gap filled patterned conduc...

HSQ with high plasma etching resistance surface for borderless vias

HSQ with high plasma etching resistance surface for borderless vias

Borderless vias with HSQ gap filled patterned metal layers

High density plasma oxide gap filled patterned metal layers with im...

Method of prevention of degradation of low dielectric constant gap-...

Electromigration resistant patterned metal layer gap filled with HSQ

Vacuum baked HSQ gap fill layer for high integrity borderless vias

Selective etching for improved dielectric interlayer planarization

Reduced cracking in gap filling dielectrics

High integrity borderless vias with protective sidewall spacer

Tapered isolated metal profile to reduce dielectric layer cracking

Borderless vias with HSQ gap filled metal patterns having high etch...

Borderless vias

HSQ baking for reduced dielectric constant

HSQ processing for reduced dielectric constant

Borderless vias with HSQ gap filled patterned metal layers

Patents Applicationslast 30 patents

LASER PATTERNED SOLID-STATE BATTERIES, AND METHODS OF MAKING AND US...

CYLINDRICAL SOLID-STATE BATTERY, AND METHODS OF MAKING AND USING TH...

HIGH ENERGY-DENSITY SOLID-STATE BATTERY, AND METHOD(S) OF MAKING TH...

PASSIVATION/ENCAPSULATION LAYER, VIA AND DISTRIBUTION LAYER, SOLID-...

Wafer processing apparatus and method

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25U AND SMALLER SEMI...

Wafer processing apparatus and method

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMA...

Method for reducing stress-induced voids for 0.25mμ and smal...