Kibby B Horsford

Person

Essex, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Producing wafer level packaging using leadframe strip and related d...
- Patent number 10,304,763
- Issue date May 28, 2019
- GLOBALFOUNDRIES Inc.
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Producing wafer level packaging using leadframe strip and related d...
- Patent number 9,892,999
- Issue date Feb 13, 2018
- GLOBALFOUNDRIES Inc.
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level chip-scale package structure utilizing conductive polymer
- Patent number 9,496,234
- Issue date Nov 15, 2016
- GLOBALFOUNDRIES Inc.
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask and substrate alignment for solder bump process
- Patent number 7,670,437
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Duane E Allen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask and substrate alignment for solder bump process
- Patent number 7,410,919
- Issue date Aug 12, 2008
- International Business Machines Corporation
- Duane E Allen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarized plastic package modules for integrated circuits
- Patent number 6,603,195
- Issue date Aug 5, 2003
- International Business Machines Corporation
- David V. Caletka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for testing integrated circuit chips
- Patent number 5,672,980
- Issue date Sep 30, 1997
- International Business Machines Corporation
- Richard Gordon Charlton
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing integrated circuit chips
- Patent number 5,659,256
- Issue date Aug 19, 1997
- International Business Machines Corporation
- Richard Gordon Charlton
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing integrated circuit chips
- Patent number 5,528,159
- Issue date Jun 18, 1996
- International Business Machine Corp.
- Richard G. Charlton
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing integrated circuit chips
- Patent number 5,523,696
- Issue date Jun 4, 1996
- International Business Machines Corp.
- Richard G. Charlton
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED D...
- Publication number 20180122730
- Publication date May 3, 2018
- GLOBALFOUNDRIES INC.
- Richard S. GRAF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED D...
- Publication number 20170352611
- Publication date Dec 7, 2017
- GLOBALFOUNDRIES Inc.
- Richard S. GRAF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE USING POLYMER-SOLDER BALL STRUCTURES AND...
- Publication number 20170271285
- Publication date Sep 21, 2017
- GLOBALFOUNDRIES INC.
- Richard S. Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK AND SUBSTRATE ALIGNMENT FOR SOLDER BUMP PROCESS
- Publication number 20080202421
- Publication date Aug 28, 2008
- Duane E. Allen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK AND SUBSTRATE ALIGNMENT FOR SOLDER BUMP PROCESS
- Publication number 20040261977
- Publication date Dec 30, 2004
- International Business Machines Corporation
- Duane E. Allen
- H01 - BASIC ELECTRIC ELEMENTS

Kibby B Horsford

Person

Patents Grantslast 30 patents

Producing wafer level packaging using leadframe strip and related d...

Producing wafer level packaging using leadframe strip and related d...

Wafer-level chip-scale package structure utilizing conductive polymer

Mask and substrate alignment for solder bump process

Mask and substrate alignment for solder bump process

Planarized plastic package modules for integrated circuits

Method and apparatus for testing integrated circuit chips

Method and apparatus for testing integrated circuit chips

Method and apparatus for testing integrated circuit chips

Method and apparatus for testing integrated circuit chips

Patents Applicationslast 30 patents

PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED D...

PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED D...

INTEGRATED CIRCUIT PACKAGE USING POLYMER-SOLDER BALL STRUCTURES AND...

MASK AND SUBSTRATE ALIGNMENT FOR SOLDER BUMP PROCESS

MASK AND SUBSTRATE ALIGNMENT FOR SOLDER BUMP PROCESS