Patent Application
20170271285
The present disclosure relates generally to integrated circuits, and more specifically, to an integrated circuit package using polymer-solder ball structures and methods of forming the same.
Wafer-level chip-scale package (WLCSP) refers to a mechanism of packaging an integrated circuit (IC) at a wafer level, resulting in a device practically the same size as the die. An integrated circuit refers to a circuit in which a number of circuit elements are electrically connected on a single chip. Typically, integrated circuits are manufactured in large batches on a single semiconductor wafer. The large wafer contains an array of integrated circuits that is then cut such that each piece of the wafer contains a single copy of the integrated circuit. This individual copy of the integrated circuit on the wafer is known as a die. The process of cutting the large wafer into individual die is called device singulation. WLCSP provides a solder inter-connection directly between a device and an end product's motherboard.
WLCSP processing includes wafer bumping (with or without pad layer redistribution or redistribution layer (RDL)), wafer level final testing, device singulation, and packing in tape and reel. Wafer bumping refers to the process of forming solder balls on the wafer. A redistribution layer is a metal layer of the integrated circuit configured to enable contact with the input/output (I/O) pads of the integrated circuit at a different location. Device singulation, as explained above, refers to the process of cutting, dicing, or otherwise dividing an array of integrated circuits into individual integrated circuits. Some of the most widely offered WLCSP options include WLCSP bump on pad (BOP) and WLCSP with a redistribution layer (RDL).
The WLCSP bump on pad (BOP) option provides a reliable, cost-effective, true chip-size package on devices not requiring redistribution. Under-bump-metallurgy (UBM) is added and solder bumps are then placed directly over die I/O pads. WLCSP-BOP is designed to utilize industry-standard surface mount assembly and reflow techniques.
The WLCSP with a redistribution layer (RDL) option adds a plated copper RDL to route I/O pads to standard pitches such as those promulgated by the Joint Electron Device Engineering Council (JEDEC)/Electronic Industries Association of Japan (EIAJ) (JEDEC/EIAJ). Such monitoring avoids the need to redesign legacy parts for CSP applications. A nickel-based or thick copper UBM, along with polyimide or polybenzoxazole (PBO) dielectrics, provide improved board level reliability performance such as mechanical stability of the bump and reliable electronic connection between the solder bump and the I/O pad. WLCSP with RDL utilizes industry-standard surface mount assembly and reflow techniques, and does not require underfill on qualified device size and I/O layouts.
WLCSP has seen significant growth as a true chip scale package, by allowing direct chip attach of a flip chip die without underfill. WLCSP has also seen significant growth for mobile and smart phone applications, especially for power management IC's. However, WLCSP is restricted to systems having a relatively small die size and a low I/O count.
In one illustrative embodiment, a conductive polymer-solder ball structure is provided. The conductive polymer-solder ball structure includes a wafer having a substrate layer and at least one metal pad providing an electrically conductive path to the substrate layer; a conductive polymer pad located directly on the wafer over the at least one metal pad; an electrolessly plated layer over and contacting the conductive polymer pad; and a solder ball over and contacting the electrolessly plated layer.
In another illustrative embodiment, a method is provided for creating a conductive polymer-solder ball structure. The method includes forming at least one conductive polymer pad to a wafer, the wafer having at least one metal pad configured to provide an electrical conductive path to a substrate layer of the wafer; electrolessly plating a layer of conductive material to a surface of at least one of the at least one conductive polymer pads; and dropping a solder ball on at least one of the electrolessly plated layers.
In yet another illustrative embodiment, an integrated circuit package including one or more conductive polymer-solder ball structures is provided. Each conductive polymer-solder ball structure including a wafer having a substrate layer and at least one metal pad providing an electrical conductive path to the substrate layer; a conductive polymer pad located directly on the wafer over the at least one metal pad; an electrolessly plated layer located on a surface of the conductive polymer pad; and a solder ball located on a surface of the electrolessly plated layer.
The present disclosure, as well as the preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
These and other features and advantages of the present disclosure will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description.
As stated previously, wafer-level chip-scale packaging (WLCSP) refers to a technology of packaging an integrated circuit at a wafer level, resulting in a device practically the same size as the die. However, current WLCSP is constrained by two major factors: chip size and bump pitch/density. With regard to chip size, WLCSP requires that all bumps must be contained within the chip footprint, and it is not economically feasible to grow chip size in order to increase the number of bumps. With regard to bump pitch/density, reducing the bump size/pitch increases bump density, but reducing the size of the bump also reduces the reliability. While redistribution layers may be added to relocate the bumps to a location other than the location of I/O pads, the redistribution layers also causes a significant cost increase. Illustrative embodiments provide a screen printed conductive polymer base for a WLCSP solder bump, which improves reliability as well as enables larger chip sizes to utilize the WLCSP solution without the need to add an additional redistribution layer to the wafer.
The present description and claims may make use of the terms “a,” “at least one of,” and “one or more of” with regard to particular features and elements of the illustrative embodiments. It should be appreciated that these terms and phrases are intended to state that there is at least one of the particular feature or element present in the particular illustrative embodiment, but that more than one can also be present. That is, these terms/phrases are not intended to limit the description or claims to a single feature/element being present or require that a plurality of such features/elements be present. To the contrary, these terms/phrases only require at least a single feature/element with the possibility of a plurality of such features/elements being within the scope of the description and claims.
A dielectric is a non-conducting-material or substance. (A dielectric is an electrical insulator.) Some dielectrics commonly used in semiconductor technology are SiO2 (silicon dioxide or “oxide”) and Si3N4 (silicon nitride or “nitride”).
Metal pad structures 106 may include aluminum, gold, copper, or any other electrically conductive metal or combinations of metals now known or later developed. Wafer structure 100 also includes a passivation dielectric layer 108 applied to the other locations on wafer structure 100 where the one or more solder ball structures will not be formed. Passivation dielectric layer 108 may include a hard oxide material, nitride, or any other dielectric material now know or later developed.
Dielectric layer 104 includes chip back end of line (BEOL) features. BEOL refers to operations performed on the semiconductor wafer in the course of device manufacturing following first metallization. Dielectric layer 104 may potentially include numerous metal layers and passivation layers as well as a low-k dielectric, which is a material with a small dielectric constant relative to silicon dioxide. As is illustrated, metal pad structures 106 may be electrically connected to any layer between metal pad 106 and substrate 102 using vias 110. As is further illustrated, passivation dielectric layer 108 may also be applied to outer portions of one or more metal pad structures 106 in order to provide structural support for metal pad structures 106.
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Thus, the illustrative embodiments provide for a screen-printed conductive polymer base for a WLCSP solder bump 120, 220, which improves reliability as well as enables larger chip sizes to utilize the WLCSP solution without the need to add an additional redistribution layer to the wafer. One or more conductive polymer pads are applied to a wafer structure at locations on the wafer structure where one or more solder ball structures will be formed. Portions of the one or more conductive polymer pad structures are masked off and a photoresist layer 116, 216 is applied to the wafer. Then, the portions of the one or more conductive polymer pad structures that were masked off are opened up to expose the top of one or more conductive polymer pad structures 114, 214 and an electroless plating later 118, 218 is applied to the exposed portions of the one or more conductive polymer pad structures. Finally, a solder ball 120, 220 is formed on each of the electrolessly plated layers thereby forming the one or more solder ball structures. Creating a screen printed conductive polymer base for a WLCSP in this way lowers the cost as compared to a double redistribution layer method while improving reliability. The illustrated process also allows for growth of chip size or reduction of WLCSP bump size/pitch. For WLCSP to be joined to next level assembly, the wafer must be thinned and each chip must be diced out.
The present disclosure is presented for purposed of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The embodiments were chosen and described in order to best explain the principles of the present disclosure, the practical application, and to enable others of ordinary skill in the art to understand the present disclosure for various embodiments with various modifications as are suited to the particular use contemplated. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
