Kimin Jun

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Monolithic chip stacking using a die with double-sided interconnect...
- Patent number 12,362,325
- Issue date Jul 15, 2025
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Liquid cooled interposer for integrated circuit stack
- Patent number 12,300,579
- Issue date May 13, 2025
- Intel Corporation
- Georgios Dogiamis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact structures and fabrication for metal on both sides...
- Patent number 12,288,810
- Issue date Apr 29, 2025
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitors and resistors at direct bonding interfaces in microelect...
- Patent number 12,266,682
- Issue date Apr 1, 2025
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned interconnect structures and methods of fabrication
- Patent number 12,266,570
- Issue date Apr 1, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct bonding in microelectronic assemblies
- Patent number 12,199,018
- Issue date Jan 14, 2025
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies
- Patent number 12,176,323
- Issue date Dec 24, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies with inductors in direct bonding regions
- Patent number 12,107,060
- Issue date Oct 1, 2024
- Intel Corproation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,761
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,762
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies with inductors in direct bonding regions
- Patent number 12,062,631
- Issue date Aug 13, 2024
- Intel Corporation
- Adel A Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact structures and fabrication for metal on both sides...
- Patent number 11,935,933
- Issue date Mar 19, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization structures for stacked device connectivity and their...
- Patent number 11,869,894
- Issue date Jan 9, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device structures and double-sided electrical te...
- Patent number 11,854,894
- Issue date Dec 26, 2023
- Intel Corporation
- Valluri R. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic chip stacking using a die with double-sided interconnect...
- Patent number 11,784,165
- Issue date Oct 10, 2023
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies
- Patent number 11,721,649
- Issue date Aug 8, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors having device strata with different channel widths
- Patent number 11,676,966
- Issue date Jun 13, 2023
- Intel Corporation
- Gilbert W. Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact structures and fabrication for metal on both sides...
- Patent number 11,658,221
- Issue date May 23, 2023
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V source/drain in top NMOS transistors for low temperature stac...
- Patent number 11,640,961
- Issue date May 2, 2023
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuits with stacked transistors
- Patent number 11,605,565
- Issue date Mar 14, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication and use of through silicon vias on double sided interco...
- Patent number 11,594,524
- Issue date Feb 28, 2023
- Intel Corporation
- Brennen K. Mueller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for revealing a backside of an integrated circuit device...
- Patent number 11,594,452
- Issue date Feb 28, 2023
- Intel Corporation
- Il-Seok Son
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical memory cells
- Patent number 11,569,238
- Issue date Jan 31, 2023
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with dielectric between channels of different d...
- Patent number 11,552,104
- Issue date Jan 10, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors on heterogeneous bonding layers
- Patent number 11,532,719
- Issue date Dec 20, 2022
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked CMOS with upfront M0 interconnect
- Patent number 11,482,621
- Issue date Oct 25, 2022
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization structures for stacked device connectivity and their...
- Patent number 11,430,814
- Issue date Aug 30, 2022
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with Si PMOS and high mobility thin film transi...
- Patent number 11,393,818
- Issue date Jul 19, 2022
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies
- Patent number 11,393,777
- Issue date Jul 19, 2022
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY ARCHITECTURES WITH HYBRID BONDING
- Publication number 20250220925
- Publication date Jul 3, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...
- Publication number 20250220952
- Publication date Jul 3, 2025
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONFIGURABLE CARRIER FOR TRANSFER AND SELF-ASSEMBLY OF MULTIPLE INT...
- Publication number 20250218847
- Publication date Jul 3, 2025
- Intel Corporation
- Veronica A. Strong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HANDLING ASSEMBLY, HANDLING SYSTEM AND METHOD
- Publication number 20250210392
- Publication date Jun 26, 2025
- Intel Corporation
- Bhaskar Jyoti KRISHNATREYA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...
- Publication number 20250112077
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES
- Publication number 20250112127
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES
- Publication number 20250112173
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES
- Publication number 20250112199
- Publication date Apr 3, 2025
- Intel Corporation
- Thomas Sounart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...
- Publication number 20250112200
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONFORMAL COATINGS WITH SPATIALLY DEFINED SURFACE ENERGIES FOR DIE-...
- Publication number 20250112155
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT
- Publication number 20250112187
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID B...
- Publication number 20250112177
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
- Publication number 20250112208
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER
- Publication number 20250108459
- Publication date Apr 3, 2025
- Intel Corporation
- Andrey Vyatskikh
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASS...
- Publication number 20250112181
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE
- Publication number 20250112186
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
- Publication number 20250112196
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS
- Publication number 20250112218
- Publication date Apr 3, 2025
- Intel Corporation
- Brandon M. Rawlings
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITORS FOR USE WITH INTEGRATED CIRCUIT PACKAGES
- Publication number 20250105136
- Publication date Mar 27, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE LAYER TRANSFER
- Publication number 20250105046
- Publication date Mar 27, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES
- Publication number 20250070083
- Publication date Feb 27, 2025
- Intel Corporation
- Adel A. ELSHERBINI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING
- Publication number 20250006678
- Publication date Jan 2, 2025
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARCHITECTURE INCLUDING COMPENSATION LAYERS FOR WAFER-SCAL...
- Publication number 20250006695
- Publication date Jan 2, 2025
- Intel Corporation
- Bhaskar Jyoti Krishnatreya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20240413237
- Publication date Dec 12, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS
- Publication number 20240355768
- Publication date Oct 24, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...
- Publication number 20240194533
- Publication date Jun 13, 2024
- Intel Corporation
- Valluri R. RAO
- G01 - MEASURING TESTING
Information Patent Application
BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...
- Publication number 20240154011
- Publication date May 9, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE, METHOD, AND SYSTEM TO PROTECT THROUGH-DIELECTRIC VIAS OF A...
- Publication number 20240063147
- Publication date Feb 22, 2024
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC DIE COMPOSITES WITH INORGANIC INTER-DIE FILL STRUCTURES
- Publication number 20240063180
- Publication date Feb 22, 2024
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUASI-MONOLITHIC DIE ARCHITECTURES
- Publication number 20240063178
- Publication date Feb 22, 2024
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Monolithic chip stacking using a die with double-sided interconnect...

Liquid cooled interposer for integrated circuit stack

Backside contact structures and fabrication for metal on both sides...

Capacitors and resistors at direct bonding interfaces in microelect...

Self-aligned interconnect structures and methods of fabrication

Direct bonding in microelectronic assemblies

Microelectronic assemblies

Microelectronic assemblies with inductors in direct bonding regions

Wrap-around source/drain method of making contacts for backside metals

Wrap-around source/drain method of making contacts for backside metals

Microelectronic assemblies with inductors in direct bonding regions

Three-dimensional integrated circuits (3DICs) including bottom gate...

Backside contact structures and fabrication for metal on both sides...

Metallization structures for stacked device connectivity and their...

Integrated circuit device structures and double-sided electrical te...

Monolithic chip stacking using a die with double-sided interconnect...

Microelectronic assemblies

Stacked transistors having device strata with different channel widths

Backside contact structures and fabrication for metal on both sides...

III-V source/drain in top NMOS transistors for low temperature stac...

Three dimensional integrated circuits with stacked transistors

Fabrication and use of through silicon vias on double sided interco...

Techniques for revealing a backside of an integrated circuit device...

Vertical memory cells

Stacked transistors with dielectric between channels of different d...

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Metallization structures for stacked device connectivity and their...

Stacked transistors with Si PMOS and high mobility thin film transi...

Microelectronic assemblies

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY ARCHITECTURES WITH HYBRID BONDING

BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...

CONFIGURABLE CARRIER FOR TRANSFER AND SELF-ASSEMBLY OF MULTIPLE INT...

HANDLING ASSEMBLY, HANDLING SYSTEM AND METHOD

ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...

IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES

PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES

SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES

HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...

CONFORMAL COATINGS WITH SPATIALLY DEFINED SURFACE ENERGIES FOR DIE-...

IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT

SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID B...

SELECTIVE LAYER TRANSFER WITH GLASS PANELS

PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER

BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASS...

TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE

SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES

SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS

CAPACITORS FOR USE WITH INTEGRATED CIRCUIT PACKAGES

SELECTIVE LAYER TRANSFER

MICROELECTRONIC ASSEMBLIES

PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING

PACKAGING ARCHITECTURE INCLUDING COMPENSATION LAYERS FOR WAFER-SCAL...

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...

BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...

DEVICE, METHOD, AND SYSTEM TO PROTECT THROUGH-DIELECTRIC VIAS OF A...

IC DIE COMPOSITES WITH INORGANIC INTER-DIE FILL STRUCTURES

QUASI-MONOLITHIC DIE ARCHITECTURES