Kiran B. Buch

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for verifying timing in a hard-wired IC device modeled from...
- Patent number 6,625,788
- Issue date Sep 23, 2003
- Xilinx, Inc.
- Mehul Vashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardwire logic device emulating any of two or more FPGAs
- Patent number 6,353,921
- Issue date Mar 5, 2002
- Xilinx, Inc.
- Edwin S. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable IC with gate array core and boundary scan capability
- Patent number 6,226,779
- Issue date May 1, 2001
- Xilinx, Inc.
- Glenn A. Baxter
- G01 - MEASURING TESTING
Information Patent Grant
Method for verifying timing in a hard-wired IC device modeled from...
- Patent number 6,219,819
- Issue date Apr 17, 2001
- Xilinx, Inc.
- Mehul Vashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of implementing a boundary scan chain
- Patent number 6,134,517
- Issue date Oct 17, 2000
- Xilinx, Inc.
- Glenn A. Baxter
- G01 - MEASURING TESTING
Information Patent Grant
Hardwire logic device emulating an FPGA
- Patent number 6,120,551
- Issue date Sep 19, 2000
- Xilinx, Inc.
- Edwin S. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable I/O cell with dual boundary scan
- Patent number 6,071,314
- Issue date Jun 6, 2000
- Xilinx, Inc.
- Glenn A. Baxter
- G01 - MEASURING TESTING
Information Patent Grant
Test methodology based on multiple skewed scan clocks
- Patent number 6,070,260
- Issue date May 30, 2000
- Xilinx, Inc.
- Kiran B. Buch
- G01 - MEASURING TESTING
Information Patent Grant
Boundary scan chain with dedicated programmable routing
- Patent number 5,991,908
- Issue date Nov 23, 1999
- Xilinx, Inc.
- Glenn A. Baxter
- G01 - MEASURING TESTING
Information Patent Grant
Mask-programmed integrated circuits having timing and logic compati...
- Patent number 5,550,839
- Issue date Aug 27, 1996
- Xilinx, Inc.
- Kiran B. Buch
- G06 - COMPUTING CALCULATING COUNTING

Kiran B. Buch

Person

Patents Grantslast 30 patents

Method for verifying timing in a hard-wired IC device modeled from...

Hardwire logic device emulating any of two or more FPGAs

Programmable IC with gate array core and boundary scan capability

Method for verifying timing in a hard-wired IC device modeled from...

Method of implementing a boundary scan chain

Hardwire logic device emulating an FPGA

Programmable I/O cell with dual boundary scan

Test methodology based on multiple skewed scan clocks

Boundary scan chain with dedicated programmable routing

Mask-programmed integrated circuits having timing and logic compati...