Klaus M. Hummler

Person

Apex, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Through substrate via formation processing using sacrificial material
- Patent number 8,614,145
- Issue date Dec 24, 2013
- Sematech, Inc.
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package with interconnected stacked chips
- Patent number 8,138,610
- Issue date Mar 20, 2012
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory refresh system and method
- Patent number 7,975,170
- Issue date Jul 5, 2011
- Qimonda AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure of expanding, upgrading, or fixing multi-chip...
- Patent number 7,944,047
- Issue date May 17, 2011
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for synchronizing memory enabled systems with...
- Patent number 7,882,324
- Issue date Feb 1, 2011
- Qimonda AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal routing on redistribution layer
- Patent number 7,725,862
- Issue date May 25, 2010
- Qimonda AG
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for implementing memory enabled systems using...
- Patent number 7,721,010
- Issue date May 18, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-diagnostic scheme for detecting errors
- Patent number 7,694,196
- Issue date Apr 6, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure to share internally generated voltages between chips in MCP
- Patent number 7,688,665
- Issue date Mar 30, 2010
- Qimonda North America Corp.
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory configured on a common substrate
- Patent number 7,539,034
- Issue date May 26, 2009
- Qimonda North America Corp.
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having parity error correction
- Patent number 7,471,569
- Issue date Dec 30, 2008
- Infineon Technologies AG
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory having parity error correction
- Patent number 7,440,309
- Issue date Oct 21, 2008
- Infineon Technologies AG
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for trimming voltage or current references
- Patent number 7,423,445
- Issue date Sep 9, 2008
- Qimonda North America Corp.
- Richard Lewison
- G11 - INFORMATION STORAGE
Information Patent Grant
Data inversion device and method
- Patent number 7,420,862
- Issue date Sep 2, 2008
- Infineon Technologies AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Repair of semiconductor memory device via external command
- Patent number 7,401,270
- Issue date Jul 15, 2008
- Infineon Technologies AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal routing on redistribution layer
- Patent number 7,391,107
- Issue date Jun 24, 2008
- Infineon Technologies AG
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory having parity generation circuit
- Patent number 7,382,673
- Issue date Jun 3, 2008
- Infineon Technologies AG
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECC flag for testing on-chip error correction circuit
- Patent number 7,373,583
- Issue date May 13, 2008
- Infineon Technologies North America Corp.
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access using multiple activated memory cell rows
- Patent number 7,272,070
- Issue date Sep 18, 2007
- Infineon Technologies AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible internal address counting method and apparatus
- Patent number 7,164,613
- Issue date Jan 16, 2007
- Infineon Technologies AG
- Khaled Fekih-Romdhane
- G11 - INFORMATION STORAGE
Information Patent Grant
Top oxide nitride liner integration scheme for vertical DRAM
- Patent number 7,091,553
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top oxide nitride liner integration scheme for vertical DRAM
- Patent number 6,972,266
- Issue date Dec 6, 2005
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory cell
- Patent number 6,873,003
- Issue date Mar 29, 2005
- Infineon Technologies Aktiengesellschaft
- Daniele Casarotto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SiGe vertical gate contact for gate conductor post etch treatment
- Patent number 6,740,558
- Issue date May 25, 2004
- Infineon Technologies AB
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with deep trench isolation and method of manuf...
- Patent number 6,734,059
- Issue date May 11, 2004
- Infineon Technologies AG
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for back-side contact for trench semiconductor de...
- Patent number 6,724,030
- Issue date Apr 20, 2004
- Infineon Technologies North American Corp.
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a gate electrode contact spacer for a vertical DR...
- Patent number 6,673,686
- Issue date Jan 6, 2004
- Infineon Technologies AG
- Arnd R. Scholz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Support liner for isolation trench height control in vertical DRAM...
- Patent number 6,620,677
- Issue date Sep 16, 2003
- Infineon Technologies AG
- Klaus M. Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for achieving high self-aligning vertical gate studs relativ...
- Patent number 6,617,213
- Issue date Sep 9, 2003
- Infineon Technologies AG
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer assisted trench top isolation for vertical DRAM's
- Patent number 6,586,300
- Issue date Jul 1, 2003
- Infineon Technologies AG
- Klaus M. Hummler
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HETEROGENEOUS STACK STRUCTURES WITH OPTICAL TO ELECTRICAL TIMING RE...
- Publication number 20130320359
- Publication date Dec 5, 2013
- SEMATECH, INC.
- Klaus HUMMLER
- G02 - OPTICS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH BURIED THROUGH SUBSTRATE VIAS
- Publication number 20130299950
- Publication date Nov 14, 2013
- SEMATECH, INC.
- Klaus HUMMLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING THROUGH SUBSTRATE VIAS
- Publication number 20130157436
- Publication date Jun 20, 2013
- SEMATECH, INC.
- Klaus HUMMLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE
- Publication number 20090200652
- Publication date Aug 13, 2009
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS
- Publication number 20090129186
- Publication date May 21, 2009
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...
- Publication number 20090113158
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...
- Publication number 20090113078
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...
- Publication number 20090079055
- Publication date Mar 26, 2009
- JONG HOON OH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
- Publication number 20090080279
- Publication date Mar 26, 2009
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY REFRESH SYSTEM AND METHOD
- Publication number 20080313494
- Publication date Dec 18, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL ROUTING ON REDISTRIBUTION LAYER
- Publication number 20080220607
- Publication date Sep 11, 2008
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory configured on a common substrate
- Publication number 20080189480
- Publication date Aug 7, 2008
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for trimming voltage or current references
- Publication number 20080012596
- Publication date Jan 17, 2008
- Richard Lewison
- G01 - MEASURING TESTING
Information Patent Application
Data inversion device and method
- Publication number 20070250657
- Publication date Oct 25, 2007
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Repair of semiconductor memory device via external command
- Publication number 20070113121
- Publication date May 17, 2007
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Signal routing on redistribution layer
- Publication number 20070042591
- Publication date Feb 22, 2007
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory having parity error correction
- Publication number 20060285410
- Publication date Dec 21, 2006
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory having parity generation circuit
- Publication number 20060285409
- Publication date Dec 21, 2006
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory having parity error correction
- Publication number 20060285412
- Publication date Dec 21, 2006
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ECC flag for testing on-chip error correction circuit
- Publication number 20060282747
- Publication date Dec 14, 2006
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Optimized testing of on-chip error correction circuit
- Publication number 20060265636
- Publication date Nov 23, 2006
- Klaus Hummler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory access using multiple activated memory cell rows
- Publication number 20060133186
- Publication date Jun 22, 2006
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Flexible internal address counting method and apparatus
- Publication number 20060109735
- Publication date May 25, 2006
- Khaled Fekih-Romdhane
- G11 - INFORMATION STORAGE
Information Patent Application
Top oxide nitride liner integration scheme for vertical DRAM
- Publication number 20050196919
- Publication date Sep 8, 2005
- International Buisiness Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a trench structure
- Publication number 20050170661
- Publication date Aug 4, 2005
- International Business Machines Corporation
- Laertis Economikos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP OXIDE NITRIDE LINER INTEGRATION SCHEME FOR VERTICAL DRAM
- Publication number 20050070108
- Publication date Mar 31, 2005
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NONVOLATILE MEMORY CELL
- Publication number 20040173839
- Publication date Sep 9, 2004
- Daniele Casarotto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND METHOD OF MANUF...
- Publication number 20040097029
- Publication date May 20, 2004
- Infineon Technologies North America Corp.
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGE VERTICAL GATE CONTACT FOR GATE CONDUCTOR POST ETCH TREATMENT
- Publication number 20040097039
- Publication date May 20, 2004
- Infineon Technologies North America Corp.
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIV...
- Publication number 20030143809
- Publication date Jul 31, 2003
- Infineon Technologies North America Corp.
- Klaus Hummler
- H01 - BASIC ELECTRIC ELEMENTS

Klaus M. Hummler

Person

Patents Grantslast 30 patents

Through substrate via formation processing using sacrificial material

Multi-chip package with interconnected stacked chips

Memory refresh system and method

Method and structure of expanding, upgrading, or fixing multi-chip...

Method and apparatus for synchronizing memory enabled systems with...

Signal routing on redistribution layer

Method and apparatus for implementing memory enabled systems using...

Self-diagnostic scheme for detecting errors

Structure to share internally generated voltages between chips in MCP

Memory configured on a common substrate

Memory having parity error correction

Memory having parity error correction

Method and system for trimming voltage or current references

Data inversion device and method

Repair of semiconductor memory device via external command

Signal routing on redistribution layer

Memory having parity generation circuit

ECC flag for testing on-chip error correction circuit

Memory access using multiple activated memory cell rows

Flexible internal address counting method and apparatus

Top oxide nitride liner integration scheme for vertical DRAM

Top oxide nitride liner integration scheme for vertical DRAM

Nonvolatile memory cell

SiGe vertical gate contact for gate conductor post etch treatment

Semiconductor device with deep trench isolation and method of manuf...

System and method for back-side contact for trench semiconductor de...

Method of forming a gate electrode contact spacer for a vertical DR...

Support liner for isolation trench height control in vertical DRAM...

Method for achieving high self-aligning vertical gate studs relativ...

Spacer assisted trench top isolation for vertical DRAM&#x00027;s

Patents Applicationslast 30 patents

HETEROGENEOUS STACK STRUCTURES WITH OPTICAL TO ELECTRICAL TIMING RE...

SEMICONDUCTOR STRUCTURE WITH BURIED THROUGH SUBSTRATE VIAS

FORMING THROUGH SUBSTRATE VIAS

METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE

SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS

METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...

METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...

METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...

STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP

MEMORY REFRESH SYSTEM AND METHOD

SIGNAL ROUTING ON REDISTRIBUTION LAYER

Memory configured on a common substrate

Method and system for trimming voltage or current references

Data inversion device and method

Repair of semiconductor memory device via external command

Signal routing on redistribution layer

Memory having parity error correction

Memory having parity generation circuit

Memory having parity error correction

ECC flag for testing on-chip error correction circuit

Optimized testing of on-chip error correction circuit

Memory access using multiple activated memory cell rows

Flexible internal address counting method and apparatus

Top oxide nitride liner integration scheme for vertical DRAM

Method of forming a trench structure

TOP OXIDE NITRIDE LINER INTEGRATION SCHEME FOR VERTICAL DRAM

NONVOLATILE MEMORY CELL

SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND METHOD OF MANUF...

SIGE VERTICAL GATE CONTACT FOR GATE CONDUCTOR POST ETCH TREATMENT

METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIV...

Spacer assisted trench top isolation for vertical DRAM's