Klaus Nierle

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for manufacturing a multiple-chip memory devic...
- Patent number 8,468,401
- Issue date Jun 18, 2013
- Qimonda AG
- KoonHee Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for addressing errors in a multiple-chip memory d...
- Patent number 7,802,133
- Issue date Sep 21, 2010
- Qimonda North America Corp.
- KoonHee Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for testing an integrated circuit
- Patent number 7,729,186
- Issue date Jun 1, 2010
- Qimonda AG
- Joerg Kliewer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for increasing clock frequency and data rate f...
- Patent number 7,385,872
- Issue date Jun 10, 2008
- Qimonda North America Corp.
- Klaus Nierle
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode method and apparatus for internal memory timing signals
- Patent number 7,339,841
- Issue date Mar 4, 2008
- Infineon Technologies AG
- Martin Versen
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial presence detect functionality on memory component
- Patent number 7,263,019
- Issue date Aug 28, 2007
- Infineon Technologies AG
- Klaus Nierle
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for full wafer contact probing, wafer design and probe card...
- Patent number 7,157,923
- Issue date Jan 2, 2007
- Infineon Technologies AG
- Peter Schneider
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing the serviceability of bit lines in a DRAM memory...
- Patent number 7,120,070
- Issue date Oct 10, 2006
- Infineon Technologies AG
- Martin Versen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for varying an active duty cycle of a wordline
- Patent number 7,072,234
- Issue date Jul 4, 2006
- Infineon Technologies AG
- Klaus Nierle
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and Method for Manufacturing a Multiple-Chip Memory Device
- Publication number 20100306605
- Publication date Dec 2, 2010
- QIMONDA NORTH AMERICA CORP.
- KoonHee Lee
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for addressing errors in a multiple-chip memory d...
- Publication number 20090006887
- Publication date Jan 1, 2009
- QIMONDA NORTH AMERICA CORP.
- KoonHee Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for stressing upper level interconnects in semic...
- Publication number 20080285358
- Publication date Nov 20, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Nierle
- G01 - MEASURING TESTING
Information Patent Application
Method and circuit for stressing upper level interconnects in semic...
- Publication number 20080237587
- Publication date Oct 2, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Nierle
- G11 - INFORMATION STORAGE
Information Patent Application
Method and System for Testing an Integrated Circuit
- Publication number 20080205173
- Publication date Aug 28, 2008
- Joerg Kliewer
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR INCREASING CLOCK FREQUENCY AND DATA RATE F...
- Publication number 20080089164
- Publication date Apr 17, 2008
- Klaus Nierle
- G11 - INFORMATION STORAGE
Information Patent Application
Test mode method and apparatus for internal memory timing signals
- Publication number 20070064505
- Publication date Mar 22, 2007
- Martin Versen
- G11 - INFORMATION STORAGE
Information Patent Application
Serial presence detect functionality on memory component
- Publication number 20070058470
- Publication date Mar 15, 2007
- Klaus Nierle
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Testmode and test method for increased stress duty cycles during bu...
- Publication number 20070038804
- Publication date Feb 15, 2007
- Klaus Nierle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test method, control circuit and system for reduced time combined w...
- Publication number 20060136791
- Publication date Jun 22, 2006
- Klaus Nierle
- G11 - INFORMATION STORAGE
Information Patent Application
Method for full wafer contact probing, wafer design and probe card...
- Publication number 20060103401
- Publication date May 18, 2006
- Peter Schneider
- G01 - MEASURING TESTING
Information Patent Application
Method for testing the serviceability of bit lines in a DRAM memory...
- Publication number 20060048022
- Publication date Mar 2, 2006
- Martin Versen
- G11 - INFORMATION STORAGE
Information Patent Application
Internal data generation and compare via unused external pins
- Publication number 20040133827
- Publication date Jul 8, 2004
- International Business Machines Corporation
- Alan D. Norris
- G11 - INFORMATION STORAGE

Klaus Nierle

Person

Patents Grantslast 30 patents

Apparatus and method for manufacturing a multiple-chip memory devic...

System and method for addressing errors in a multiple-chip memory d...

Method and system for testing an integrated circuit

Method and apparatus for increasing clock frequency and data rate f...

Test mode method and apparatus for internal memory timing signals

Serial presence detect functionality on memory component

Method for full wafer contact probing, wafer design and probe card...

Method for testing the serviceability of bit lines in a DRAM memory...

Method and device for varying an active duty cycle of a wordline

Patents Applicationslast 30 patents

Apparatus and Method for Manufacturing a Multiple-Chip Memory Device

System and method for addressing errors in a multiple-chip memory d...

Method and circuit for stressing upper level interconnects in semic...

Method and circuit for stressing upper level interconnects in semic...

Method and System for Testing an Integrated Circuit

METHOD AND APPARATUS FOR INCREASING CLOCK FREQUENCY AND DATA RATE F...

Test mode method and apparatus for internal memory timing signals

Serial presence detect functionality on memory component

Testmode and test method for increased stress duty cycles during bu...

Test method, control circuit and system for reduced time combined w...

Method for full wafer contact probing, wafer design and probe card...

Method for testing the serviceability of bit lines in a DRAM memory...

Internal data generation and compare via unused external pins