Patent Application
20080237587
Defects and failures occur during the manufacture of semiconductor devices. A “failure” occurs when a semiconductor device fails to meet specifications. A “defect” occurs when a semiconductor device has an improper circuit structure that currently presents a failure of the device, or has the potential to cause failure during the expected lifetime of the device. Defects can occur in interconnects that are arranged between conductive layers within a semiconductor device. A defect in interconnects may not occur when the semiconductor device is produced, but such a defect has the potential to fail (e.g., short) during the expected lifetime of the semiconductor device.
During manufacture of semiconductor devices, voids are formed during the deposition of the necessary layers on a substrate, which include interconnects. As circuit density on semiconductor devices increases, the size of interconnects becomes smaller. A void in smaller interconnects is more likely to cause a short during the life expectancy of the semiconductor device. Such a short can cause an open circuit or a reduced voltage within the semiconductor device, and thus results in failure of the semiconductor device.
With the advent of Very Large Scale Integration (VLSI), many integrated circuit designs include several circuit functions on a single semiconductor substrate, such as memory storage and logic components for addressing and accessing the memory. In the case where a logic region and a dynamic random access memory (DRAM) are formed on the same substrate, the circuitry is commonly referred to as an embedded DRAM. In a DRAM, a plurality of conductor layers can be arranged above the actual memory cell array. One of these conductor layers can be connected to the WL-on potential and another connected to the WL drive circuit. Interconnects are arranged between these conductor layers, allowing the precharge of the WL-on potential to charge the word lines of the memory cells. Interconnects can also be used between the bit lines of DRAM.
Functional problems caused by voids in the upper level interconnects on DRAM containing semiconductor devices occur in certain instances at a very late state of the product life time and can not easily be detected or effectively stressed during semiconductor manufacturing. This is the case for the word line (WL) drive wiring, because the capacitive load of the WL is not large enough to establish a stress current which is sufficiently high to aggravate the marginality of the current path of the WL drive circuit.
Testing is performed on semiconductor devices to identify defects and failures. A conventional approach to testing interconnects involves operating the DRAM word line control in a nominal fashion while elevating the internal voltages by executing of a series of word line activate-precharge sequences. However, this approach only has a very limited effect on marginal connections, such as interconnects. This past approach is not suitable for aggravating or stressing defective connections to a level that results in an open circuit or unacceptably reduced voltage and that is easily detected during a following product testing.
A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements and which together with a detailed description set forth herein are incorporated in and form part of the specification, serve to further illustrate various exemplary embodiments and to explain various principles and advantages in accordance with this application.
The following exemplary embodiments and aspects thereof are described and illustrated in conjunction with structures and methods that are meant to be exemplary and illustrative, and not limiting in scope. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments described in this application. In specific embodiments, circuits are shown in block diagram form in order not to obscure the embodiments described in this application in unnecessary detail. For the most part, details have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the embodiments described in this application.
The embodiments of this application relate to a method and circuit for stressing interconnects formed between conductive layers in a semiconductor device. These embodiments include stressing interconnects contained within an array of dynamic random access memories (DRAMs), such as where interconnects that supply voltage to the word lines or bit lines of the memory array are arranged between conductive layers. These embodiments also include stressing interconnects arranged within any semiconductor device, such as those including logic components and memory storage devices other than DRAMs, for example, SDRAM (synchronous DRAM), SRAM (static random access memory), as well as stand alone RAM (random access memory). These embodiments further include stressing interconnects within VLSI devices where several circuit functions are provided on a single semiconductor substrate, such as memory storage and logic components for addressing and accessing the memory.
In the memory device 100 shown in
In the embodiment of
While five conductive layers 130 and 140-143 and four interconnects 151-153 are shown, a larger number of conductive layers and interconnects can be used, as understood by those skilled in the art, depending on the size and configuration of the memory array, logic chips, etc., as desired. The conductive layers and interconnects can be made of doped polysilicon, doped amorphous silicon, germanium silicon, titanium nitride, a metallic material (such as an AlCu alloy), composites thereof, or a like conductive material.
The circuit shown in
The logic command 161 of the test circuitry can provide the necessary address and control signals to the row (WL) decoder 110 to properly activate a word line of the memory device 100. This includes sequentially or incrementally addressing word lines in a memory array. The logic command 161 also can provide a reset signal to the WL-reset controller 115 for resetting the word lines via the WL reset switches 102.
The test mode can be activated by a test control signal, such as a chip select signal, received on the test pin 162. The test pin 162 can be associated with pins on the semiconductor device other than the precharge pin and pins associated with word line operations. For example, the test pin 162 can be associated with the chip select pin, address pin, column address select (CAS), etc. When the test mode is enabled, the WL precharge device (such as WL reset switches 102) is controlled utilizing an external pin control. At the same time, the logic command 161 controls the voltage regulator 170 to reduce the WL-on potential voltage level to a level that avoids overstressing components within the WL driver current path other than the interconnect.
During test mode, the voltage regulator 170 supplies the test voltage to the stress path for a period of time A, which is independent of normal word line functioning. In other words, the WL precharge device is not coupled with timing limitations associated with normal word line operations during test mode, but rather can provide a cross current from the WL-on potential to the WL-off potential for a period of time A sufficient for stressing the interconnect lines in the WL drive circuit. The period of time A can be arbitrarily adjusted to a time sufficient for stressing the interconnect, while not damaging components of the memory device 100 within the stressing path other than the interconnect. In a typical stressing method, the test voltage is reduced to less than the nominal voltage, and the period of time A is increased to a time longer than that for normal word line operations.
A representative stress (or stressing) path is shown in
In the embodiment illustrated in
A method of stressing an interconnect according to one embodiment can be summarized as follows:
In 306, it is determined if the current word line is the last word line to be stressed. If no, the word line address is incremented to the next word line address in 307. From 307, the method returns to 302 for activating the next word line and stressing the path associated with the next word line including another or a different interconnect. If the answer in 306 is yes (the stress path of the last word line was competed), the method proceeds to 308 and ends. In a typical stressing method, all the word lines in the memory array will be individually and consecutively selected, so that interconnects associated with all the word lines are stressed.
In the embodiment shown in
After the stressing of interconnects is complete, the semiconductor device can be tested by known methods to determine if any interconnects failed. For example, conventional testing of memory can be administered, where predetermined data or voltage values are applied to selected word line and bit line addresses, which correspond to certain memory cells to store or “write” data in the cells. Then, voltage values are read from such memory cells to determine if the data read matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses or interconnects associated therewith likely contain defects, and the semiconductor devices fail the test.
The foregoing description of the embodiments of the present invention is presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above description. The scope of the invention is to be defined only by the claims appended hereto, as may be amended during the pendency of this application for patent, and all equivalents thereof.
Some embodiments can include a plurality of processes or steps, which can be performed in any order, unless expressly and necessarily limited to a particular order. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims.
