Kuljit S. BAINS

Person

Olympia, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reduction of latency impact of on-die error checking and correction...
- Patent number 12,181,966
- Issue date Dec 31, 2024
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory chip with per row activation count having error correction c...
- Patent number 12,164,373
- Issue date Dec 10, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 12,087,352
- Issue date Sep 10, 2024
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Inline buffer for in-memory post package repair (PPR)
- Patent number 11,989,106
- Issue date May 21, 2024
- Intel Corporation
- Jongwon Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read retry to selectively disable on-die ECC
- Patent number 11,966,286
- Issue date Apr 23, 2024
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology to provide accurate training and per-bit deskew capabili...
- Patent number 11,954,360
- Issue date Apr 9, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Undo and redo of soft post package repair
- Patent number 11,837,314
- Issue date Dec 5, 2023
- SK Hynix NAND Product Solutions Corp.
- Bill Nale
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,776,619
- Issue date Oct 3, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory wordline isolation for improvement in reliability, availabil...
- Patent number 11,704,194
- Issue date Jul 18, 2023
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing persistent write operations usi...
- Patent number 11,650,765
- Issue date May 16, 2023
- QUALCOMM Incorporated
- Raj Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,557,333
- Issue date Jan 17, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 11,335,395
- Issue date May 17, 2022
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Read retry to selectively disable on-die ECC
- Patent number 11,314,589
- Issue date Apr 26, 2022
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory wordline isolation for improvement in reliability, availabil...
- Patent number 11,210,167
- Issue date Dec 28, 2021
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing persistent write operations usi...
- Patent number 11,194,524
- Issue date Dec 7, 2021
- QUALCOMM Incorporated
- Raj Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with local cache array
- Patent number 11,144,466
- Issue date Oct 12, 2021
- Intel Corporation
- Jongwon Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,056,179
- Issue date Jul 6, 2021
- Intel Corporation
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Persistent write data for energy-backed memory
- Patent number 11,016,669
- Issue date May 25, 2021
- QUALCOMM Incorporated
- Kuljit Singh Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write credits management for non-volatile memory
- Patent number 10,996,888
- Issue date May 4, 2021
- QUALCOMM Incorporated
- Kuljit Singh Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die ECC with error counter and internal address generation
- Patent number 10,949,296
- Issue date Mar 16, 2021
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, method and system for providing termination for multiple...
- Patent number 10,943,640
- Issue date Mar 9, 2021
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for a per-DRAM addressability mode
- Patent number 10,902,890
- Issue date Jan 26, 2021
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing single data rate (SDR) mode or double data rate (DDR) mod...
- Patent number 10,884,639
- Issue date Jan 5, 2021
- QUALCOMM Incorporated
- Liyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal error checking and correction (ECC) with extra system bits
- Patent number 10,872,011
- Issue date Dec 22, 2020
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 10,839,887
- Issue date Nov 17, 2020
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device error check and scrub mode and error transparency
- Patent number 10,810,079
- Issue date Oct 20, 2020
- Intel Corporation
- John B Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to mirror a command/address or interpret command/address...
- Patent number 10,802,532
- Issue date Oct 13, 2020
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate command bus
- Patent number 10,789,010
- Issue date Sep 29, 2020
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable on-die termination timing in a multi-rank system
- Patent number 10,680,613
- Issue date Jun 9, 2020
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20250006250
- Publication date Jan 2, 2025
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
RUNTIME ALERT SIGNAL ACTIVATION TEST MODE
- Publication number 20240404617
- Publication date Dec 5, 2024
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
IN-SYSTEM MITIGATION OF UNCORRECTABLE ERRORS BASED ON CONFIDENCE FA...
- Publication number 20240241778
- Publication date Jul 18, 2024
- Intel Corporation
- Shen ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20240222347
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING
- Publication number 20240211344
- Publication date Jun 27, 2024
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...
- Publication number 20240061741
- Publication date Feb 22, 2024
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20240029785
- Publication date Jan 25, 2024
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
DATA LINE (DQ) SPARING WITH ADAPTIVE ERROR CORRECTION CODING (ECC)...
- Publication number 20240013851
- Publication date Jan 11, 2024
- Intel Corporation
- Hang CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
FOUR WAY PSEUDO SPLIT DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHI...
- Publication number 20230393740
- Publication date Dec 7, 2023
- Intel Corporation
- Todd A. HINCK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE AND ACCESS OF METADATA WITHIN SELECTIVE DYNAMIC RANDOM ACCE...
- Publication number 20230333928
- Publication date Oct 19, 2023
- Intel Corporation
- Todd HINCK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE ECC MODE IN DRAM
- Publication number 20230223096
- Publication date Jul 13, 2023
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
ASSESSING RISK OF FUTURE UNCORRECTABLE MEMORY ERRORS WITH FULLY COR...
- Publication number 20230086101
- Publication date Mar 23, 2023
- Cong Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNCORRECTABLE MEMORY ERROR PREDICTION
- Publication number 20230083193
- Publication date Mar 16, 2023
- Intel Corporation
- Shen ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO IMPLEMENT HALF WIDTH MODES IN DRAM AND DOUBLING OF BANK R...
- Publication number 20230013181
- Publication date Jan 19, 2023
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY STRUCTURE FOR LOW TEMPERATURE OPERATION
- Publication number 20230005921
- Publication date Jan 5, 2023
- Intel Corporation
- Sagar SUTHRAM
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM DESIGN FOR LOW TEMPERATURE MEMORY
- Publication number 20230005526
- Publication date Jan 5, 2023
- Intel Corporation
- Sagar SUTHRAM
- G11 - INFORMATION STORAGE
Information Patent Application
UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION
- Publication number 20220393682
- Publication date Dec 8, 2022
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME SPARING FOR UNCORRECTABLE ERRORS BASED ON FAULT-AWARE ANALYSIS
- Publication number 20220350715
- Publication date Nov 3, 2022
- Intel Corporation
- Shen ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED CONTROLLER AND MEMORY TO STORE MEMORY ERROR INFORMATION
- Publication number 20220350500
- Publication date Nov 3, 2022
- Intel Corporation
- Wei P. CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY
- Publication number 20220262428
- Publication date Aug 18, 2022
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC
- Publication number 20220229724
- Publication date Jul 21, 2022
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFECT ROW HAMMER TRACKING WITH MULTIPLE COUNT INCREMENTS
- Publication number 20220121398
- Publication date Apr 21, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PER BANK REFRESH HAZARD AVOIDANCE FOR LARGE SCALE MEMORY
- Publication number 20220108743
- Publication date Apr 7, 2022
- Intel Corporation
- Chang Kian TAN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WORDLINE ISOLATION FOR IMPROVEMENT IN RELIABILITY, AVAILABIL...
- Publication number 20220075689
- Publication date Mar 10, 2022
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE OFFLINING BASED ON FAULT-AWARE PREDICTION OF IMMINENT MEMORY E...
- Publication number 20220050603
- Publication date Feb 17, 2022
- Intel Corporation
- Shen ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PERFORMING PERSISTENT WRITE OPERATIONS USI...
- Publication number 20220050600
- Publication date Feb 17, 2022
- QUALCOMM Incorporated
- Raj RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PER CHANNEL THERMAL MANAGEMENT TECHNIQUES FOR STACKED MEMORY
- Publication number 20220011960
- Publication date Jan 13, 2022
- Intel Corporation
- Chang Kian TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CONFIGURATION OF MEMORY MODULE DATA WIDTH
- Publication number 20220012173
- Publication date Jan 13, 2022
- Intel Corporation
- Duane E. GALBI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING LOGIC FOR FLEXIBLE CONFIGURATION OF MEMORY MODULE DATA WIDTH
- Publication number 20220012195
- Publication date Jan 13, 2022
- Intel Corporation
- Duane E. GALBI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...
- Publication number 20210365316
- Publication date Nov 25, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING

Kuljit S. BAINS

Person

Patents Grantslast 30 patents

Reduction of latency impact of on-die error checking and correction...

Memory chip with per row activation count having error correction c...

Techniques to couple high bandwidth memory device on silicon substr...

Inline buffer for in-memory post package repair (PPR)

Read retry to selectively disable on-die ECC

Technology to provide accurate training and per-bit deskew capabili...

Undo and redo of soft post package repair

Techniques to couple high bandwidth memory device on silicon substr...

Memory wordline isolation for improvement in reliability, availabil...

Apparatus and method for performing persistent write operations usi...

Techniques to couple high bandwidth memory device on silicon substr...

Applying chip select for memory device identification and power man...

Read retry to selectively disable on-die ECC

Memory wordline isolation for improvement in reliability, availabil...

Apparatus and method for performing persistent write operations usi...

Memory device with local cache array

Techniques to couple high bandwidth memory device on silicon substr...

Persistent write data for energy-backed memory

Write credits management for non-volatile memory

On-die ECC with error counter and internal address generation

Apparatus, method and system for providing termination for multiple...

Method, apparatus and system for a per-DRAM addressability mode

Providing single data rate (SDR) mode or double data rate (DDR) mod...

Internal error checking and correction (ECC) with extra system bits

Applying chip select for memory device identification and power man...

Memory device error check and scrub mode and error transparency

Techniques to mirror a command/address or interpret command/address...

Double data rate command bus

Programmable on-die termination timing in a multi-rank system

Techniques to access or operate a dual in-line memory module via mu...

Patents Applicationslast 30 patents

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

RUNTIME ALERT SIGNAL ACTIVATION TEST MODE

IN-SYSTEM MITIGATION OF UNCORRECTABLE ERRORS BASED ON CONFIDENCE FA...

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING

ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

DATA LINE (DQ) SPARING WITH ADAPTIVE ERROR CORRECTION CODING (ECC)...

FOUR WAY PSEUDO SPLIT DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHI...

STORAGE AND ACCESS OF METADATA WITHIN SELECTIVE DYNAMIC RANDOM ACCE...

CONFIGURABLE ECC MODE IN DRAM

ASSESSING RISK OF FUTURE UNCORRECTABLE MEMORY ERRORS WITH FULLY COR...

UNCORRECTABLE MEMORY ERROR PREDICTION

METHOD TO IMPLEMENT HALF WIDTH MODES IN DRAM AND DOUBLING OF BANK R...

MEMORY STRUCTURE FOR LOW TEMPERATURE OPERATION

SYSTEM DESIGN FOR LOW TEMPERATURE MEMORY

UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION

RUNTIME SPARING FOR UNCORRECTABLE ERRORS BASED ON FAULT-AWARE ANALYSIS

EMBEDDED CONTROLLER AND MEMORY TO STORE MEMORY ERROR INFORMATION

METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY

READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC

PERFECT ROW HAMMER TRACKING WITH MULTIPLE COUNT INCREMENTS

PER BANK REFRESH HAZARD AVOIDANCE FOR LARGE SCALE MEMORY

MEMORY WORDLINE ISOLATION FOR IMPROVEMENT IN RELIABILITY, AVAILABIL...

PAGE OFFLINING BASED ON FAULT-AWARE PREDICTION OF IMMINENT MEMORY E...

APPARATUS AND METHOD FOR PERFORMING PERSISTENT WRITE OPERATIONS USI...

PER CHANNEL THERMAL MANAGEMENT TECHNIQUES FOR STACKED MEMORY

FLEXIBLE CONFIGURATION OF MEMORY MODULE DATA WIDTH

ENABLING LOGIC FOR FLEXIBLE CONFIGURATION OF MEMORY MODULE DATA WIDTH

MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...