Kulwinder Dhanoa

Person

Old Windsor, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for predictive scheduling and rate limiting
- Patent number 11,431,646
- Issue date Aug 30, 2022
- Intel Corporation
- Kulwinder Singh Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for predictive scheduling and rate limiting
- Patent number 10,834,009
- Issue date Nov 10, 2020
- Intel Corporation
- Kulwinder Singh Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
SDRAM memory organization and efficient access
- Patent number 9,424,210
- Issue date Aug 23, 2016
- Altera Corporation
- Benjamin Thomas Cope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for interfacing between hard logic and soft log...
- Patent number 9,000,802
- Issue date Apr 7, 2015
- Altera Corporation
- Michael Fitton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hardware architecture and scheduling for high performance and low r...
- Patent number 8,782,115
- Issue date Jul 15, 2014
- Altera Corporation
- Kulwinder Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Downlink subchannelization module
- Patent number 8,731,078
- Issue date May 20, 2014
- Altera Corporation
- Kulwinder Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for interfacing between hard logic and soft log...
- Patent number 8,629,691
- Issue date Jan 14, 2014
- Altera Corporation
- Michael Fitton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ranging code detection
- Patent number 8,548,078
- Issue date Oct 1, 2013
- Altera Corporation
- Michael Fitton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Solving linear matrices in an integrated circuit device
- Patent number 8,539,014
- Issue date Sep 17, 2013
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture and scheduling for high performance solution...
- Patent number 8,307,021
- Issue date Nov 6, 2012
- Altera Corporation
- Kulwinder Dhanoa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ranging code detection
- Patent number 8,121,203
- Issue date Feb 21, 2012
- Altera Corporation
- Michael Fitton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Peak windowing for crest factor reduction
- Patent number 8,005,177
- Issue date Aug 23, 2011
- Altera Corporation
- Volker Mauer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Downlink subchannelization module
- Patent number 7,983,350
- Issue date Jul 19, 2011
- Altera Corporation
- Kulwinder Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interleaving and deinterleaving involving concatenation of wor...
- Patent number 7,954,015
- Issue date May 31, 2011
- Altera Corporation
- Kulwinder Dhanoa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controller having a buffer for providing beginning and end data
- Patent number 7,899,957
- Issue date Mar 1, 2011
- Altera Corporation
- Kulwinder Dhanoa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peak windowing for crest factor reduction
- Patent number 7,586,995
- Issue date Sep 8, 2009
- Altera Corporation
- Volker Mauer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital data error insertion methods and apparatus
- Patent number 7,321,996
- Issue date Jan 22, 2008
- Altera Corporation
- Andrew Draper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller
- Patent number 7,159,084
- Issue date Jan 2, 2007
- Altera Corporation
- Kulwinder Dhanoa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for shared memory interfaces in programmable...
- Patent number 6,828,822
- Issue date Dec 7, 2004
- Altera Corporation
- Andrew J. Bellis
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR PREDICTIVE SCHEDULING AND RATE LIMITING
- Publication number 20210083986
- Publication date Mar 18, 2021
- Intel Corporation
- Kulwinder Singh Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR PREDICTIVE SCHEDULING AND RATE LIMITING
- Publication number 20190215277
- Publication date Jul 11, 2019
- Intel Corporation
- Kulwinder Singh Dhanoa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...
- Publication number 20140125379
- Publication date May 8, 2014
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...
- Publication number 20120319730
- Publication date Dec 20, 2012
- Altera Corporation
- Michael Fitton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOLVING LINEAR MATRICES IN AN INTEGRATED CIRCUIT DEVICE
- Publication number 20110238720
- Publication date Sep 29, 2011
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING

Kulwinder Dhanoa

Person

Patents Grantslast 30 patents

Systems and methods for predictive scheduling and rate limiting

Systems and methods for predictive scheduling and rate limiting

SDRAM memory organization and efficient access

Systems and methods for interfacing between hard logic and soft log...

Hardware architecture and scheduling for high performance and low r...

Downlink subchannelization module

Systems and methods for interfacing between hard logic and soft log...

Ranging code detection

Solving linear matrices in an integrated circuit device

Hardware architecture and scheduling for high performance solution...

Ranging code detection

Peak windowing for crest factor reduction

Downlink subchannelization module

Data interleaving and deinterleaving involving concatenation of wor...

Memory controller having a buffer for providing beginning and end data

Peak windowing for crest factor reduction

Digital data error insertion methods and apparatus

Memory controller

Apparatus and methods for shared memory interfaces in programmable...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR PREDICTIVE SCHEDULING AND RATE LIMITING

SYSTEMS AND METHODS FOR PREDICTIVE SCHEDULING AND RATE LIMITING

SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...

SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOG...

SOLVING LINEAR MATRICES IN AN INTEGRATED CIRCUIT DEVICE