Kumar Sudarshan

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low power content addressable memory
- Patent number 11,017,858
- Issue date May 25, 2021
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to limit current-change induced voltage change...
- Patent number 7,685,451
- Issue date Mar 23, 2010
- Intel Corporation
- James S. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-clocked domino circuits with reduced leakage current
- Patent number 6,952,118
- Issue date Oct 4, 2005
- Intel Corporation
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Patent number 6,833,735
- Issue date Dec 21, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for improving the performance of a floating po...
- Patent number 6,820,106
- Issue date Nov 16, 2004
- Intel Corporation
- Narsing K. Vijayrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power entry latch to interface static logic with dynamic logic
- Patent number 6,707,318
- Issue date Mar 16, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power precharge scheme for memory bit lines
- Patent number 6,631,093
- Issue date Oct 7, 2003
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for low power memory bit line precharge
- Patent number 6,629,194
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-entry register cell
- Patent number 6,628,539
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual threshold voltage complementary pass-transistor logic implemen...
- Patent number 6,615,229
- Issue date Sep 2, 2003
- Intel Corporation
- Narsing Vijayrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for low power domino decoding
- Patent number 6,593,776
- Issue date Jul 15, 2003
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power clock buffer with shared, precharge transistor
- Patent number 6,369,616
- Issue date Apr 9, 2002
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing soft errors in dynamic circuits
- Patent number 6,351,151
- Issue date Feb 26, 2002
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing power consumption in a data storage device
- Patent number 6,341,099
- Issue date Jan 22, 2002
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing soft errors in dynamic circuits
- Patent number 6,292,029
- Issue date Sep 18, 2001
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed four-to-two carry save adder
- Patent number 6,266,757
- Issue date Jul 24, 2001
- Intel Corporation
- Mehul Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast 2-input 32-bit domino adder
- Patent number 6,205,463
- Issue date Mar 20, 2001
- Intel Corporation
- Rajesh Manglore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power clock buffer with shared, clocked transistor
- Patent number 6,127,850
- Issue date Oct 3, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock buffer having a reduced, clocked, pull-down transistor
- Patent number 6,124,737
- Issue date Sep 26, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power multiplexer with shared, clocked transistor
- Patent number 6,111,435
- Issue date Aug 29, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Broken stack priority encoder
- Patent number 6,058,403
- Issue date May 2, 2000
- Intel Corporation
- Narsing K. Vijayrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for verifying hold time in integrated circuit design
- Patent number 6,023,767
- Issue date Feb 8, 2000
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating carries in an adder circuit
- Patent number 5,944,777
- Issue date Aug 31, 1999
- Intel Corporation
- Sanjay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing a high speed tristate buffer
- Patent number 5,900,744
- Issue date May 4, 1999
- Intel Corporation
- Bharat K. Bisen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS sum select incrementor
- Patent number 5,889,693
- Issue date Mar 30, 1999
- Intel Corporation
- Vivek Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Positive feedback circuit for fast domino logic
- Patent number 5,661,675
- Issue date Aug 26, 1997
- Intel Corporation
- Kai J. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast parity generator using complement pass-transistor logic
- Patent number 5,608,741
- Issue date Mar 4, 1997
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry skip adder with enhanced grouping scheme
- Patent number 5,581,497
- Issue date Dec 3, 1996
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast static CMOS adder
- Patent number 5,579,254
- Issue date Nov 26, 1996
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast static CMOS adder
- Patent number 5,471,414
- Issue date Nov 28, 1995
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low Power Content Addressable Memory
- Publication number 20220013154
- Publication date Jan 13, 2022
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
FAST MATRIX MULTIPLICATION
- Publication number 20220012304
- Publication date Jan 13, 2022
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power and low cost projection system
- Publication number 20120057135
- Publication date Mar 8, 2012
- Sudarshan Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Publication number 20040124882
- Publication date Jul 1, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus to limit current-change induced voltage change...
- Publication number 20040120445
- Publication date Jun 24, 2004
- James S. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gate-clocked domino circuits with reduced leakage current
- Publication number 20040119503
- Publication date Jun 24, 2004
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low power entry latch to interface static logic with dynamic logic
- Publication number 20030184344
- Publication date Oct 2, 2003
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for low power domino decoding
- Publication number 20030025531
- Publication date Feb 6, 2003
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES
- Publication number 20030002382
- Publication date Jan 2, 2003
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for low power memory bit line precharge
- Publication number 20020184431
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-entry register cell
- Publication number 20020181268
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing soft errors in dynamic circuits
- Publication number 20010040467
- Publication date Nov 15, 2001
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY

Kumar Sudarshan

Person

Patents Grantslast 30 patents

Low power content addressable memory

Method and apparatus to limit current-change induced voltage change...

Gate-clocked domino circuits with reduced leakage current

Single stage pulsed domino circuit for driving cascaded skewed stat...

Method and apparatus for improving the performance of a floating po...

Low power entry latch to interface static logic with dynamic logic

Low power precharge scheme for memory bit lines

Method and apparatus for low power memory bit line precharge

Multi-entry register cell

Dual threshold voltage complementary pass-transistor logic implemen...

Method and apparatus for low power domino decoding

Low power clock buffer with shared, precharge transistor

Method and apparatus for reducing soft errors in dynamic circuits

Reducing power consumption in a data storage device

Method and apparatus for reducing soft errors in dynamic circuits

High speed four-to-two carry save adder

Fast 2-input 32-bit domino adder

Low power clock buffer with shared, clocked transistor

Low power clock buffer having a reduced, clocked, pull-down transistor

Low power multiplexer with shared, clocked transistor

Broken stack priority encoder

Method for verifying hold time in integrated circuit design

Method and apparatus for generating carries in an adder circuit

Method and apparatus for providing a high speed tristate buffer

CMOS sum select incrementor

Positive feedback circuit for fast domino logic

Fast parity generator using complement pass-transistor logic

Carry skip adder with enhanced grouping scheme

Fast static CMOS adder

Fast static CMOS adder

Patents Applicationslast 30 patents

Low Power Content Addressable Memory

FAST MATRIX MULTIPLICATION

Low power and low cost projection system

Single stage pulsed domino circuit for driving cascaded skewed stat...

Method and apparatus to limit current-change induced voltage change...

Gate-clocked domino circuits with reduced leakage current

Low power entry latch to interface static logic with dynamic logic

Method and apparatus for low power domino decoding

LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES

Method and apparatus for low power memory bit line precharge

Multi-entry register cell

Method and apparatus for reducing soft errors in dynamic circuits