Lance E. Hacking

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Schedule-aware tensor distribution module
- Patent number 11,907,827
- Issue date Feb 20, 2024
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating neural networks with low precision-based multiplicatio...
- Patent number 11,714,998
- Issue date Aug 1, 2023
- Intel Corporation
- Avishaii Abuhatzera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, apparatus, articles of manufacture to perform accelerated...
- Patent number 11,347,828
- Issue date May 31, 2022
- Intel Corporation
- Biji George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for dynamic power management of memories
- Patent number 9,830,954
- Issue date Nov 28, 2017
- Intel Corporation
- Lance E. Hacking
- G11 - INFORMATION STORAGE
Information Patent Grant
Debug interface
- Patent number 9,372,768
- Issue date Jun 21, 2016
- Intel Corporation
- Jeremy Conner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface logic for a multi-core system-on-a-chip (SoC)
- Patent number 9,189,439
- Issue date Nov 17, 2015
- Intel Corporation
- Ramana Rachakonda
- G01 - MEASURING TESTING
Information Patent Grant
Technique for monitoring activity within an integrated circuit
- Patent number 9,189,302
- Issue date Nov 17, 2015
- Intel Corporation
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for monitoring activity within an integrated circuit
- Patent number 8,656,411
- Issue date Feb 18, 2014
- Intel Corporation
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface logic for a multi-core system-on-a-chip (SoC)
- Patent number 8,650,629
- Issue date Feb 11, 2014
- Intel Corporation
- Ramana Rachakonda
- G01 - MEASURING TESTING
Information Patent Grant
Write combining protocol between processors and chipsets
- Patent number 8,412,855
- Issue date Apr 2, 2013
- Intel Corporation
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing idle leakage power in an IC
- Patent number 8,392,728
- Issue date Mar 5, 2013
- Intel Corporation
- Lance Hacking
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Technique for promoting determinism among multiple clock domains
- Patent number 8,312,309
- Issue date Nov 13, 2012
- Intel Corporation
- Eric L. Hendrickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect bandwidth throttler
- Patent number 8,289,850
- Issue date Oct 16, 2012
- Intel Corporation
- Lance Hacking
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Interconnect bandwidth throttler
- Patent number 8,050,177
- Issue date Nov 1, 2011
- Intel Corporation
- Lance Hacking
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power mode control method and circuitry
- Patent number 7,877,619
- Issue date Jan 25, 2011
- Ramana Rachakonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interconnect switching mechanism
- Patent number 7,707,350
- Issue date Apr 27, 2010
- Intel Corporation
- Michael E. Altenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write combining protocol between processors and chipsets
- Patent number 7,676,603
- Issue date Mar 9, 2010
- Intel Corporation
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
P-state feedback to operating system with hardware coordination
- Patent number 7,360,103
- Issue date Apr 15, 2008
- Intel Corporation
- Bernard J. Lint
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power state coordination between devices sharing power-managed reso...
- Patent number 7,315,952
- Issue date Jan 1, 2008
- Intel Corporation
- Jeffrey R. Wilcox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for synchronizing load operations
- Patent number 7,284,118
- Issue date Oct 16, 2007
- Intel Corporation
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coordination of power management activities
- Patent number 7,272,741
- Issue date Sep 18, 2007
- Intel Corporation
- Jeffrey R. Wilcox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Globally observing load operations prior to fence instruction and p...
- Patent number 7,249,245
- Issue date Jul 24, 2007
- Intel Corporation
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing cache segment flush and cache s...
- Patent number 6,978,357
- Issue date Dec 20, 2005
- Intel Corporation
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of load operations using load fence instruction in...
- Patent number 6,862,679
- Issue date Mar 1, 2005
- Intel Corporation
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing more than 4 Gigabytes of physica...
- Patent number 6,289,431
- Issue date Sep 11, 2001
- Intel Corporation
- Bryant E. Bigbee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of weakly ordered write combining operations using...
- Patent number 6,073,210
- Issue date Jun 6, 2000
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set extension using prefixes
- Patent number 6,014,735
- Issue date Jan 11, 2000
- Intel Corporation
- Srinivas Chennupaty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory attribute palette
- Patent number 5,946,713
- Issue date Aug 31, 1999
- Intel Corporation
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Schedule-Aware Tensor Distribution Module
- Publication number 20240220785
- Publication date Jul 4, 2024
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING NEURAL NETWORKS WITH LOW PRECISION-BASED MULTIPLICATIO...
- Publication number 20240005135
- Publication date Jan 4, 2024
- Intel Corporation
- Avishaii Abuhatzera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Schedule-Aware Tensor Distribution Module
- Publication number 20200410327
- Publication date Dec 31, 2020
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING NEURAL NETWORKS WITH LOW PRECISION-BASED MULTIPLICATIO...
- Publication number 20200320375
- Publication date Oct 8, 2020
- Intel Corporation
- Avishaii Abuhatzera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS, ARTICLES OF MANUFACTURE TO PERFORM ACCELERATED...
- Publication number 20200226203
- Publication date Jul 16, 2020
- Intel Corporation
- Biji George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE PROCESSOR ELEMENT ARRAYS FOR IMPLEMENTING CONVOLUTIONA...
- Publication number 20200134417
- Publication date Apr 30, 2020
- Intel Corporation
- Debabrata Mohapatra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR FEATURE DETECTION AND TRACKING
- Publication number 20180189587
- Publication date Jul 5, 2018
- Intel Corporation
- Dipan Kumar Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG INTERFACE
- Publication number 20150186232
- Publication date Jul 2, 2015
- Jeremy Conner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for Monitoring Activity within an Integrated Circuit
- Publication number 20140149999
- Publication date May 29, 2014
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC)
- Publication number 20140108695
- Publication date Apr 17, 2014
- Ramana Rachakonda
- G01 - MEASURING TESTING
Information Patent Application
INTERCONNECT BANDWIDTH THROTTLER
- Publication number 20140108684
- Publication date Apr 17, 2014
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES
- Publication number 20120243364
- Publication date Sep 27, 2012
- LANCE E. HACKING
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECT BANDWIDTH THROTTLER
- Publication number 20120054387
- Publication date Mar 1, 2012
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface Logic For A Multi-Core System-On-A-Chip (SoC)
- Publication number 20110145909
- Publication date Jun 16, 2011
- Ramana Rachakonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS
- Publication number 20100332686
- Publication date Dec 30, 2010
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT BANDWIDTH THROTTLER
- Publication number 20090248927
- Publication date Oct 1, 2009
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP INTERCONNECT SWIZZLE MECHANISM
- Publication number 20090248936
- Publication date Oct 1, 2009
- Michael E. Altenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for Monitoring Activity within an Integrated Circuit
- Publication number 20090228902
- Publication date Sep 10, 2009
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for Promoting Determinism Among Multiple Clock Domains
- Publication number 20090228736
- Publication date Sep 10, 2009
- Eric L. Hendrickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MODE CONTROL METHOD AND CIRCUITRY
- Publication number 20090172429
- Publication date Jul 2, 2009
- Ramana Rachakonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING IDLE LEAKAGE POWER IN AN IC
- Publication number 20080155280
- Publication date Jun 26, 2008
- Lance Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet exchange for controlling system power modes
- Publication number 20060080461
- Publication date Apr 13, 2006
- Jeffrey R. Wilcox
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Hardware coordination of power management activities
- Publication number 20050273633
- Publication date Dec 8, 2005
- Intel Corporation
- Jeffrey R. Wilcox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power state coordination between devices sharing power-managed reso...
- Publication number 20050273635
- Publication date Dec 8, 2005
- Jeffrey R. Wilcox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
P-state feedback to operating system with hardware coordination
- Publication number 20050262365
- Publication date Nov 24, 2005
- Bernard J. Lint
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Write combining protocol between processors and chipsets
- Publication number 20050235067
- Publication date Oct 20, 2005
- Intel Corporation
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for synchronizing load operations
- Publication number 20040162969
- Publication date Aug 19, 2004
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for synchronizing load operations
- Publication number 20040162970
- Publication date Aug 19, 2004
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and a method of sorting perfomance data from one or more sys...
- Publication number 20030018960
- Publication date Jan 23, 2003
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for synchronizing load operation
- Publication number 20020112146
- Publication date Aug 15, 2002
- Lance E. Hacking
- G06 - COMPUTING CALCULATING COUNTING

Lance E. Hacking

Person

Patents Grantslast 30 patents

Schedule-aware tensor distribution module

Accelerating neural networks with low precision-based multiplicatio...

Methods, apparatus, articles of manufacture to perform accelerated...

Method and system for dynamic power management of memories

Debug interface

Interface logic for a multi-core system-on-a-chip (SoC)

Technique for monitoring activity within an integrated circuit

Technique for monitoring activity within an integrated circuit

Interface logic for a multi-core system-on-a-chip (SoC)

Write combining protocol between processors and chipsets

Reducing idle leakage power in an IC

Technique for promoting determinism among multiple clock domains

Interconnect bandwidth throttler

Interconnect bandwidth throttler

Power mode control method and circuitry

Bus interconnect switching mechanism

Write combining protocol between processors and chipsets

P-state feedback to operating system with hardware coordination

Power state coordination between devices sharing power-managed reso...

Method and apparatus for synchronizing load operations

Hardware coordination of power management activities

Globally observing load operations prior to fence instruction and p...

Method and apparatus for performing cache segment flush and cache s...

Synchronization of load operations using load fence instruction in...

Method and apparatus for accessing more than 4 Gigabytes of physica...

Synchronization of weakly ordered write combining operations using...

Instruction set extension using prefixes

Memory attribute palette

Patents Applicationslast 30 patents

Schedule-Aware Tensor Distribution Module

ACCELERATING NEURAL NETWORKS WITH LOW PRECISION-BASED MULTIPLICATIO...

Schedule-Aware Tensor Distribution Module

ACCELERATING NEURAL NETWORKS WITH LOW PRECISION-BASED MULTIPLICATIO...

METHODS, APPARATUS, ARTICLES OF MANUFACTURE TO PERFORM ACCELERATED...

CONFIGURABLE PROCESSOR ELEMENT ARRAYS FOR IMPLEMENTING CONVOLUTIONA...

TECHNOLOGIES FOR FEATURE DETECTION AND TRACKING

DEBUG INTERFACE

Technique for Monitoring Activity within an Integrated Circuit

INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC)

INTERCONNECT BANDWIDTH THROTTLER

METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES

INTERCONNECT BANDWIDTH THROTTLER

Interface Logic For A Multi-Core System-On-A-Chip (SoC)

WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS

INTERCONNECT BANDWIDTH THROTTLER

CHIP INTERCONNECT SWIZZLE MECHANISM

Technique for Monitoring Activity within an Integrated Circuit

Technique for Promoting Determinism Among Multiple Clock Domains

POWER MODE CONTROL METHOD AND CIRCUITRY

REDUCING IDLE LEAKAGE POWER IN AN IC

Packet exchange for controlling system power modes

Hardware coordination of power management activities

Power state coordination between devices sharing power-managed reso...

P-state feedback to operating system with hardware coordination

Write combining protocol between processors and chipsets

Method and apparatus for synchronizing load operations

Method and apparatus for synchronizing load operations

System and a method of sorting perfomance data from one or more sys...

Method and apparatus for synchronizing load operation