Larry Jay Thayer

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bit error rate reduction buffer, method and apparatus
- Patent number 9,298,668
- Issue date Mar 29, 2016
- Hewlett Packard Enterprise Development LP
- Larry J. Thayer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system that utilizes a wide input/output (I/O) interface to...
- Patent number 9,182,925
- Issue date Nov 10, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Repairing high-speed serial links
- Patent number 8,914,683
- Issue date Dec 16, 2014
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module and method employing a multiplexer to replace a memor...
- Patent number 8,886,892
- Issue date Nov 11, 2014
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system that utilizes a wide input/output (I/O) interface to...
- Patent number 8,634,221
- Issue date Jan 21, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods of selectively managing errors in memory modules
- Patent number 8,612,797
- Issue date Dec 17, 2013
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed interface for dynamic random access memory (DRAM)
- Patent number 8,554,991
- Issue date Oct 8, 2013
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundant memory to mask DRAM failures
- Patent number 8,473,791
- Issue date Jun 25, 2013
- Hewlett-Packard Development Company, L.P.
- Mark Shaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller
- Patent number 8,386,702
- Issue date Feb 26, 2013
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for distribution analysis of stacked-die integrat...
- Patent number 8,352,896
- Issue date Jan 8, 2013
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Larry J Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defect management for a semiconductor memory system
- Patent number 7,996,710
- Issue date Aug 9, 2011
- Hewlett-Packard Development Company, L.P.
- Dheemanth Nagaraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction algorithm selection based upon memory organization
- Patent number 7,975,205
- Issue date Jul 5, 2011
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for implementing a stride value for memory testing
- Patent number 7,844,868
- Issue date Nov 30, 2010
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit error rate reduction buffer
- Patent number 7,783,935
- Issue date Aug 24, 2010
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for implementing a stride value for accessing m...
- Patent number 7,694,193
- Issue date Apr 6, 2010
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device and system providing spare memory locat...
- Patent number 7,656,727
- Issue date Feb 2, 2010
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory correction system and method
- Patent number 7,599,235
- Issue date Oct 6, 2009
- Hewlett-Packard Development Company, L.P.
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage element for mitigating soft errors in logic
- Patent number 7,539,931
- Issue date May 26, 2009
- Hewlett-Packard Development Company, L.P.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory correction system and method
- Patent number 7,307,902
- Issue date Dec 11, 2007
- Hewlett-Packard Development Company, L.P.
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical memory correction system and method
- Patent number 7,227,797
- Issue date Jun 5, 2007
- Hewlett-Packard Development Company, L.P.
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and controller for same
- Patent number 7,103,826
- Issue date Sep 5, 2006
- Hewlett-Packard Development Company, L.P.
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAID memory system
- Patent number 7,099,994
- Issue date Aug 29, 2006
- Hewlett-Packard Development Company, L.P.
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing BLTs
- Patent number 6,943,804
- Issue date Sep 13, 2005
- Hewlett-Packard Development Company, L.P.
- Byron A. Alcorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a perspective projection in a g...
- Patent number 6,940,525
- Issue date Sep 6, 2005
- Hewlett-Packard Development Company, L.P.
- Roland M. Hochmuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for high speed bus having adjustable, symmetri...
- Patent number 6,876,224
- Issue date Apr 5, 2005
- Hewlett-Packard Development Company, L.P.
- David John Marshall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing a perspective projection in a g...
- Patent number 6,509,905
- Issue date Jan 21, 2003
- Hewlett-Packard Company
- Roland M. Hochmuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-wide texture offset addressing with page residence indicator...
- Patent number 6,362,824
- Issue date Mar 26, 2002
- Hewlett-Packard Company
- Larry J Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Corner buffer system for improved memory read efficiency during tex...
- Patent number 6,084,601
- Issue date Jul 4, 2000
- Hewlett-Packard Company
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polygon span interpolator with main memory Z buffer
- Patent number 5,493,644
- Issue date Feb 20, 1996
- Hewlett-Packard Company
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polygon renderer which determines the coordinates of polygon edges...
- Patent number 5,278,949
- Issue date Jan 11, 1994
- Hewlett-Packard Company
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE TO...
- Publication number 20140108683
- Publication date Apr 17, 2014
- Avago Technologies General IP (Singapore) PTE. LTD.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE T...
- Publication number 20130111123
- Publication date May 2, 2013
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DISTRIBUTION ANALYSIS OF STACKED-DIE INTEGRAT...
- Publication number 20120221996
- Publication date Aug 30, 2012
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED INTERFACE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM)
- Publication number 20120203961
- Publication date Aug 9, 2012
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Application
BIT ERROR RATE REDUCTION BUFFER, METHOD AND APPARATUS
- Publication number 20100275098
- Publication date Oct 28, 2010
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING A STRIDE VALUE FOR MEMORY TESTING
- Publication number 20100131810
- Publication date May 27, 2010
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPAIRING HIGH-SPEED SERIAL LINKS
- Publication number 20100083030
- Publication date Apr 1, 2010
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT MEMORY TO MASK DRAM FAILURES
- Publication number 20080270826
- Publication date Oct 30, 2008
- Mark SHAW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM
- Publication number 20080270675
- Publication date Oct 30, 2008
- Dheemanth Nagaraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCAT...
- Publication number 20080266999
- Publication date Oct 30, 2008
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR IMPLEMENTING A STRIDE VALUE FOR ACCESSING M...
- Publication number 20080229035
- Publication date Sep 18, 2008
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION ALGORITHM SELECTION BASED UPON MEMORY ORGANIZATION
- Publication number 20080184093
- Publication date Jul 31, 2008
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE AND METHOD EMPLOYING A MULTIPLEXER TO REPLACE A MEMOR...
- Publication number 20080181021
- Publication date Jul 31, 2008
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD FOR STORING AND CORRECTING DATA
- Publication number 20080077840
- Publication date Mar 27, 2008
- Mark Shaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory correction system and method
- Publication number 20080065933
- Publication date Mar 13, 2008
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bit error rate reduction buffer
- Publication number 20070300104
- Publication date Dec 27, 2007
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods of selectively managing errors in memory modules
- Publication number 20070234112
- Publication date Oct 4, 2007
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Application
Memory controller
- Publication number 20070101094
- Publication date May 3, 2007
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining hard errors vs. soft errors in memory
- Publication number 20070094569
- Publication date Apr 26, 2007
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical memory correction system and method
- Publication number 20070047344
- Publication date Mar 1, 2007
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory correction system and method
- Publication number 20070050688
- Publication date Mar 1, 2007
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power throttling system and method for a memory controller
- Publication number 20060248355
- Publication date Nov 2, 2006
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory element for mitigating soft errors in logic
- Publication number 20060236158
- Publication date Oct 19, 2006
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage element for mitigating soft errors in logic
- Publication number 20060227596
- Publication date Oct 12, 2006
- Larry J. Thayer
- G11 - INFORMATION STORAGE
Information Patent Application
RAID memory system
- Publication number 20050071554
- Publication date Mar 31, 2005
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Content addressable memory with redundant stored data
- Publication number 20050027932
- Publication date Feb 3, 2005
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system and controller for same
- Publication number 20050028069
- Publication date Feb 3, 2005
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for high speed bus having adjustable, symmetri...
- Publication number 20040085088
- Publication date May 6, 2004
- David John Marshall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for performing BLTs
- Publication number 20040085322
- Publication date May 6, 2004
- Byron A. Alcorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for preventing memory access errors
- Publication number 20030226090
- Publication date Dec 4, 2003
- Larry Jay Thayer
- G06 - COMPUTING CALCULATING COUNTING

Larry Jay Thayer

Person

Patents Grantslast 30 patents

Bit error rate reduction buffer, method and apparatus

Memory system that utilizes a wide input/output (I/O) interface to...

Repairing high-speed serial links

Memory module and method employing a multiplexer to replace a memor...

Memory system that utilizes a wide input/output (I/O) interface to...

Systems and methods of selectively managing errors in memory modules

High speed interface for dynamic random access memory (DRAM)

Redundant memory to mask DRAM failures

Memory controller

System and method for distribution analysis of stacked-die integrat...

Defect management for a semiconductor memory system

Error correction algorithm selection based upon memory organization

System and method for implementing a stride value for memory testing

Bit error rate reduction buffer

Systems and methods for implementing a stride value for accessing m...

Semiconductor memory device and system providing spare memory locat...

Memory correction system and method

Storage element for mitigating soft errors in logic

Memory correction system and method

Hierarchical memory correction system and method

Memory system and controller for same

RAID memory system

System and method for performing BLTs

Method and apparatus for performing a perspective projection in a g...

Method and apparatus for high speed bus having adjustable, symmetri...

Method and apparatus for performing a perspective projection in a g...

System-wide texture offset addressing with page residence indicator...

Corner buffer system for improved memory read efficiency during tex...

Polygon span interpolator with main memory Z buffer

Polygon renderer which determines the coordinates of polygon edges...

Patents Applicationslast 30 patents

MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE TO...

A MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE T...

SYSTEM AND METHOD FOR DISTRIBUTION ANALYSIS OF STACKED-DIE INTEGRAT...

HIGH SPEED INTERFACE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM)

BIT ERROR RATE REDUCTION BUFFER, METHOD AND APPARATUS

SYSTEM AND METHOD FOR IMPLEMENTING A STRIDE VALUE FOR MEMORY TESTING

REPAIRING HIGH-SPEED SERIAL LINKS

REDUNDANT MEMORY TO MASK DRAM FAILURES

DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM

SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCAT...

SYSTEMS AND METHODS FOR IMPLEMENTING A STRIDE VALUE FOR ACCESSING M...

ERROR CORRECTION ALGORITHM SELECTION BASED UPON MEMORY ORGANIZATION

MEMORY MODULE AND METHOD EMPLOYING A MULTIPLEXER TO REPLACE A MEMOR...

MEMORY SYSTEM AND METHOD FOR STORING AND CORRECTING DATA

Memory correction system and method

Bit error rate reduction buffer

Systems and methods of selectively managing errors in memory modules

Memory controller

Determining hard errors vs. soft errors in memory

Hierarchical memory correction system and method

Memory correction system and method

Power throttling system and method for a memory controller

Memory element for mitigating soft errors in logic

Storage element for mitigating soft errors in logic

RAID memory system

Content addressable memory with redundant stored data

Memory system and controller for same

Method and apparatus for high speed bus having adjustable, symmetri...

System and method for performing BLTs

System and method for preventing memory access errors