Larry Wissel

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Checking wafer-level integrated designs for rule compliance
- Patent number 11,170,151
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking wafer-level integrated designs for rule compliance
- Patent number 10,691,870
- Issue date Jun 23, 2020
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking wafer-level integrated designs for rule compliance
- Patent number 10,346,580
- Issue date Jul 9, 2019
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking wafer-level integrated designs for antenna rule compliance
- Patent number 10,248,755
- Issue date Apr 2, 2019
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking wafer-level integrated designs for antenna rule compliance
- Patent number 9,990,459
- Issue date Jun 5, 2018
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for conversion of commercial microprocessor to radiation-har...
- Patent number 9,646,125
- Issue date May 9, 2017
- GLOBALFOUNDRIES Inc.
- John A. Fifield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically unclonable function implemented through threshold voltag...
- Patent number 8,619,979
- Issue date Dec 31, 2013
- International Business Machines Corporation
- Joel T. Ficke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Structure for integrated circuit for measuring set-up and hold time...
- Patent number 7,930,663
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory column redundancy scheme
- Patent number 7,826,285
- Issue date Nov 2, 2010
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system of modeling leakage
- Patent number 7,793,239
- Issue date Sep 7, 2010
- International Business Machines Corporation
- James J. Engel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for improved memory column redundancy scheme
- Patent number 7,773,437
- Issue date Aug 10, 2010
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Grant
Unclocked eFUSE circuit
- Patent number 7,345,943
- Issue date Mar 18, 2008
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for programming an electrically programmable fuse
- Patent number 7,315,193
- Issue date Jan 1, 2008
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage programmable eFuse with differential sensing scheme
- Patent number 7,098,721
- Issue date Aug 29, 2006
- International Business Machines Corporation
- Michael R. Ouellette
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy register architecture for soft-error tolerance and metho...
- Patent number 7,000,155
- Issue date Feb 14, 2006
- International Business Machines Corporation
- Jeffery H. Oppold
- G11 - INFORMATION STORAGE
Information Patent Grant
Radiation tolerant flip-flop
- Patent number 6,624,677
- Issue date Sep 23, 2003
- International Business Machines Corporation
- Larry Wissel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Latch clustering for power optimization
- Patent number 6,609,228
- Issue date Aug 19, 2003
- International Business Machines Corporation
- Paul H. Bergeron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of integrated circuit design by selection of noise tolerant...
- Patent number 6,490,708
- Issue date Dec 3, 2002
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single pin performance screen ring oscillator with frequency division
- Patent number 6,426,641
- Issue date Jul 30, 2002
- International Business Machines Corporation
- Steven P. Koch
- G01 - MEASURING TESTING
Information Patent Grant
Branch isolation circuit for cascode voltage switch logic
- Patent number 5,389,836
- Issue date Feb 14, 1995
- International Business Machines Corporation
- Allan R. Bertolet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiCMOS gate pull-down circuit
- Patent number 5,118,972
- Issue date Jun 2, 1992
- International Business Machines Corporation
- Larry Wissel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE
- Publication number 20200257846
- Publication date Aug 13, 2020
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE
- Publication number 20190258771
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR ANTENNA RULE COMPLIANCE
- Publication number 20180189441
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE
- Publication number 20170277821
- Publication date Sep 28, 2017
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR ANTENNA RULE COMPLIANCE
- Publication number 20170270233
- Publication date Sep 21, 2017
- International Business Machines Corporation
- Terence B. Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HAR...
- Publication number 20140258958
- Publication date Sep 11, 2014
- International Business Machines Corporation
- John A. FIFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physically Unclonable Function Implemented Through Threshold Voltag...
- Publication number 20110317829
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Joel T. Ficke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HAR...
- Publication number 20110088008
- Publication date Apr 14, 2011
- International Business Machines Corporation
- John A. FIFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Improving Storage Latch Susceptibility to...
- Publication number 20090219752
- Publication date Sep 3, 2009
- Larry Wissel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STRUCTURE FOR IMPROVED MEMORY COLUMN REDUNDANCY SCHEME
- Publication number 20090067270
- Publication date Mar 12, 2009
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COLUMN REDUNDANCY SCHEME
- Publication number 20090067269
- Publication date Mar 12, 2009
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIME...
- Publication number 20080201675
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Larry Wissel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH...
- Publication number 20080071489
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Larry Wissel
- G01 - MEASURING TESTING
Information Patent Application
UNCLOCKED EFUSE CIRCUIT
- Publication number 20080002450
- Publication date Jan 3, 2008
- International Business Machines Corporation
- Larry Wissel
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM OF MODELING LEAKAGE
- Publication number 20070250797
- Publication date Oct 25, 2007
- James J Engel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY AND METHOD FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE FUSE
- Publication number 20070046361
- Publication date Mar 1, 2007
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy register architecture for soft-error tolerance and metho...
- Publication number 20060059393
- Publication date Mar 16, 2006
- International Business Machines Corporation
- Jeffrey H. Oppold
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME
- Publication number 20060044049
- Publication date Mar 2, 2006
- International Business Machines Corporation
- Michael R. Ouellette
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANCY REGISTER ARCHITECTURE FOR SOFT-ERROR TOLERANCE AND METHO...
- Publication number 20040210802
- Publication date Oct 21, 2004
- International Business Machines Corporation
- Jeffery H. Oppold
- G11 - INFORMATION STORAGE
Information Patent Application
A METHOD AND APPARATUS FOR INTEGRATING BOUNDARY-SCAN MULTIPLEXER FU...
- Publication number 20030115555
- Publication date Jun 19, 2003
- LARRY WISSEL
- G01 - MEASURING TESTING
Information Patent Application
Method of integrated circuit design by selection of noise tolerant...
- Publication number 20020133791
- Publication date Sep 19, 2002
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING

Larry Wissel

Person

Patents Grantslast 30 patents

Checking wafer-level integrated designs for rule compliance

Checking wafer-level integrated designs for rule compliance

Checking wafer-level integrated designs for rule compliance

Checking wafer-level integrated designs for antenna rule compliance

Checking wafer-level integrated designs for antenna rule compliance

Method for conversion of commercial microprocessor to radiation-har...

Physically unclonable function implemented through threshold voltag...

Structure for integrated circuit for measuring set-up and hold time...

Memory column redundancy scheme

Method and system of modeling leakage

Design structure for improved memory column redundancy scheme

Unclocked eFUSE circuit

Circuitry and method for programming an electrically programmable fuse

Low voltage programmable eFuse with differential sensing scheme

Redundancy register architecture for soft-error tolerance and metho...

Radiation tolerant flip-flop

Latch clustering for power optimization

Method of integrated circuit design by selection of noise tolerant...

Single pin performance screen ring oscillator with frequency division

Branch isolation circuit for cascode voltage switch logic

BiCMOS gate pull-down circuit

Patents Applicationslast 30 patents

CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE

CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE

CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR ANTENNA RULE COMPLIANCE

CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE

CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR ANTENNA RULE COMPLIANCE

METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HAR...

Physically Unclonable Function Implemented Through Threshold Voltag...

METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HAR...

Apparatus and Method for Improving Storage Latch Susceptibility to...

STRUCTURE FOR IMPROVED MEMORY COLUMN REDUNDANCY SCHEME

MEMORY COLUMN REDUNDANCY SCHEME

STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIME...

INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH...

UNCLOCKED EFUSE CIRCUIT

METHOD AND SYSTEM OF MODELING LEAKAGE

CIRCUITRY AND METHOD FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE FUSE

Redundancy register architecture for soft-error tolerance and metho...

LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME

REDUNDANCY REGISTER ARCHITECTURE FOR SOFT-ERROR TOLERANCE AND METHO...

A METHOD AND APPARATUS FOR INTEGRATING BOUNDARY-SCAN MULTIPLEXER FU...

Method of integrated circuit design by selection of noise tolerant...