BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of embodiments of the inventions, with reference to the drawings, in which:
FIG. 1A is a logical circuit diagram of one embodiment of the present invention;
FIG. 1B is a timing diagram associated with operation of the logic circuitry shown in FIG. 1, which timing diagram depicts the timing of signals required to implement a set-up test in the FIG. 1A circuitry;
FIG. 1C is a graphical representation of a locus of Delay1, and Delay2 values, which Delay1 and Delay2 values satisfy the set-up criteria associated with the logic and timing of FIGS. 1A and 1B;
FIG. 2A is a timing diagram associated with the hold-time test for the logical circuit of FIG. 1A;
FIG. 2B is a graphical representation of a locus of Delay1, and Delay2, which values satisfy the hold-time criteria associated with the logic and timing of the inventive circuitry comprising FIGS. 1A and 2A, respectively;
FIG. 2C is a combination of the limitations shown in FIGS. 1C and 2B, which describes the set-up and hold characteristics relating to the inventions disclosed herein;
FIG. 3A is a circuit diagram of a coarse delay line;
FIG. 3B is a fine delay line; and
FIG. 3C is a portion of a McLeod loop, showing how different circuit paths can be selected in order to measure the delay difference between them.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) OF THE INVENTION
The inventive methods, software and apparatus set forth herein are disclosed and described in order to convey the broad inventive concepts, claims to which are appended hereto. The drawings and descriptions are not meant to in any way limit the scope and spirit of the inventions, as claimed.
The reader is referred first to the logic circuit diagram of FIG. 1A. The logical circuit is constructed to enable determining a set-up time for flip-flop (FF1). Flip-flop set-up is the delay required for flip-flop set-up, or transition form 0 to 1, or 1 to 0. The inventive circuitry determines the flip-flop delay essentially “at” the physical location of FF1 in the IC of FIG. 2A. The logical circuitry determines the set-up time delay by adding delay to FF1 using the AddDelay signal as shown in FIG. 1B (when the polarity of the D input is 1). The AddDelay signal switches the delays in.
The set-up test thereby exactly or substantially exactly determines a delay, or aggregate delay, that is equivalent to the set-up time for FF1. The technique determines when the set-up time for FF1 is violated. To do so, the digital delay control bits (not shown in FIG. 1A) are set to 0 to define Delay1 and Delay2 as 0, or a minimum delay value. With Delay1 and Delay2 defined by respective 0-bit inputs, there is no added delay (however, there may be an inherent delay), to which the delays of Delay1 or Delay2 are added. Delay1 and Delay 2 are added after three clock cycles (AddDelay signal) as Q0, Q1, and Q2 are initialized to the same value with a single clock input (Clk0), during normal “shift register” operation (D=1). Delay0 is permanently set to match the minimum delay of Delay1.
After the three initialization clock pulses (FIG. 1B), the AddDelay signal is asserted to change the timing. Before that time, the FF1 is operating at its inherent delay. AddDelay adds Delay1 and Delay2, which may be set to minimal non-zero delay outputs or values on the next clock cycle. The next clock cycle (the fourth in the timing of FIG. 2A) is the clock cycle during which the Set-up test is performed. Q0 changes state due to the change on D, and Clk1 is delayed from Clk0. For small values of Delay1, Clk1 will still have adequate time with respect to the change of Q0, and FF1 will capture the value of Q0 from the third clock cycle (“Fail” value of Q1 in FIG. 2A). But as Delay1 is increased, the time will first be invalid. As Delay1 is increased further, Clk1 will satisfy the set-up time with regard to the new cycle-four value of Q0. A simple interpretation is that Clk1 will look like a future clock edge with regard to the transition on Q0, and that Clk1 will capture the new (cycle four) value of Q0 into FF1. This is the “Pass” value of Q1 in FIG. 1C.
The purpose of FF2 and Clk2, with respect to the FIG. 1B timing, and the FIG. 1C pass/fail diagram, is to monitor the change in delay of FF1 as its Set-up time is violated. For small values of Delay2, FF2 will always capture the cycle-three value of Q1 (“Fail” n Q2 in FIG. 2; once again, this is a set-up test). For large values of Delay2, Clk2 will be delayed from Clk1 enough that it also looks like a “future edge” with respect to the transition of Q1. FF2, therefore, will capture the new value of Q1 (“Pass” on Q2 in FIG. 1C). Delay2 has to match the Clk-Q delay of FF1 in order to capture the transition of FF1. If FF1 Clk-Q delay increases because FF1 clock (Clk1) and data (Q0) do not satisfy the Set-up time, then Delay2 will have to be increased for FF2 to capture the new value of Q1.
The “Pass SetUp” (polarity=1) condition is based on the final state of both Q1 and Q2 (FIG. 1C). More particularly, Q1 and Q2 will both be high only if Delay1 and Delay2 have proper values to capture the transitions of Q0 and Q1 into FF1 and FF2, respectively. FIG. 1C shows the locus of (Delay1, Delay2) values that separate “Pass” (both) regions from “Fail” (either) regions.
The flip-flop “hold test” (polarity=0) is very similar to the set-up delay test, initiated if the polarity input is zero (0). For the hold test, the bits Delay1 and Delay2 are set to zero (no “added” delay-only inherent delay) for three clock cycles as Q0, Q1, and Q2 are initialized in normal “shift register” operation. The tiring for the hold-test implementation is shown in FIG. 2A. After the three initialization clock pulses, the AddDelay signal is asserted to perform the Hold test on the fourth cycle. For small values of Delay1, Clk1 will have adequate hold time before the change of Q0, and FF1 will capture the value of Q0 from the third clock cycle (“Pass” value of Q1 in FIG. 2B). But as Delay1 is increased, the hold time will become invalid and ultimately FF1 will capture the cycle-four value of Q0 (“Fail” value in FIG. 2B).
Again, FF2 and Clk2 monitor the change in delay of FF1 as its Hold time is violated. For small values of Delay2, FF2 will always capture the cycle three value of Q1 (“Pass” on Q2 in FIG. 2B). For large values of Delay2, Clk2 will be delayed from Clk1 enough that it also looks like a “future edge” with respect to the transition of Q1, and FF2 will capture the cycle-four value of Q1 (“Fail” on Q2 in FIG. 1B). Delay2 has to match the Clk-Q delay of FF1 in order to capture the transition of FF1. If FF1 Clk-Q delay increases because FF1 clock (Clk1) and data (Q0) do not satisfy the Hold time, then Delay2 will have to be increased for FF2 to capture the new value of Q1. The “Pass Hold” condition is based on the final state of both Q1 and Q2. They will both be high only if Delay1 and Delay2 have proper values to capture the transitions of Q0 and Q1 into FF1 and FF2, respectively. FIG. 2C shows the locus of Delay1, Delay2) values that separate “Pass” (both) regions from “Fail” (either) regions.
A small amount of additional logic is required to implement this as a self-contained experiment with a Pass-Fail output. The “Pass” output is established with the following logic interrogated after the fourth clock:
PassSetUp=Q0.Q1.Q2+Q0′.Q1′.Q2′
PassHold=Q0′.Q1.Q2+Q0.Q1′.Q2′
Pass=TestSetUp.PassSetUp+TestSetUp′.PassHold
A four-state state machine will control this logic. The simplest form may include, for example, four state registers S[3:0] that are initialized to 0000, and are incremented through 0001, 0010, 0100, 1000 for the four cycles. The DataIn to Q0 can be generated simply as D=TestSetUp.(Test1.S2+Test1′.S2′)+TestSetUp′.[Test1.S1.S2′+Test1′.(S1.S2′)′], where “Test1” is an input that is asserted when desiring to measure the set-up or hold time with D=1, and “Test1′” is an input that is asserted when desiring to measure the set-up or hold time with D=0. The reader should note that as used herein, “′” at the end defines the “complement” of the logical operator or word. For example, Test SetUp′ is the complement of TestSetUp. TestSetUp is an input to select the set-up test, and SetUpTest′ is an input to implement the hold test. The AddDelay signal resides in the S3 register.
Delay2 of FIGS. 1C and 2B can be combined as shown FIG. 2C to fully describe the Set-up and Hold characteristics of FF1: Delay lines: Delay1 and Delay2 are set by on-chip delay lines with digital inputs. Each delay line should be a combination of coarse delay and fine delay, with the fine delay adjustment range equal to the smallest step of the coarse delay. Such delay lines are well known in the industry, with the circuit model shown in FIG. 3A representative of coarse delay, and the circuit model shown in FIG. 3B representative of fine delay.
An essential element for success for such a technique is the accurate knowledge of Delay1 and Delay2. That is, even for a fixed digital select value, these delays, that is, Delay1 and Delay2, will change with Vdd and temperature, and will certainly vary lot-to-lot and die-to-die. So it essential to include a measurement circuit. A ring oscillator with a McLeod loop of FIG. 3C is one example of a circuit that could serve this inventive purpose. For that matter, the delay line in the McLeod loop can be a replica of the delay line in the set-up and hold experiment. The skilled artisan will note, however, that although the use of a replica introduces uncertainty about the tracking of the line in the experiment, and the replica line in the loop. This uncertainty can be reduced by:
1. making the lines out of large circuits (large transistor area to reduce implant dose statistical uncertainty, and multiple-finger transistors to reduce Lpoly variation);
2. introducing additional multiplexing into the inventive circuitry, such as the FIG. 1 model, such that the delay lines used in the Clk1 and Clk2 paths are also in McLeod loops (no replicas).
It will be recognized that there are many variations possible to implement the inventions in hardware within an IC in order to accurately know the delay in a latch element or flip-flop, and communicate to support broad IC operation, e.g., shallow pipelining at very high frequency or data rates. Consequently, the examples listed above are illustrative, and not meant to be exhaustive.
Patent Application
20080071489
