LAWRENCE DOUGLAS ANDREWS, JR.

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer level surface passivation of stackable integrated circuit chips
- Patent number 8,324,081
- Issue date Dec 4, 2012
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Support mounted electrically interconnected die assembly
- Patent number 8,178,978
- Issue date May 15, 2012
- Vertical Circuits, Inc.
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flat leadless packages and stacked leadless package assemblies
- Patent number 8,159,053
- Issue date Apr 17, 2012
- Vertical Circuits, Inc.
- Lawrence Douglas Andrews, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level surface passivation of stackable integrated circuit chips
- Patent number 7,923,349
- Issue date Apr 12, 2011
- Vertical Circuits, Inc.
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flat leadless packages and stacked leadless package assemblies
- Patent number 7,843,046
- Issue date Nov 30, 2010
- Vertical Circuits, Inc.
- Lawrence Douglas Andrews, Jr.
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
- Publication number 20110147943
- Publication date Jun 23, 2011
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrically Interconnected Stacked Die Assemblies
- Publication number 20110037159
- Publication date Feb 17, 2011
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flat Leadless Packages and Stacked Leadless Package Assemblies
- Publication number 20110012246
- Publication date Jan 20, 2011
- Vertical Circuits, Inc.
- Lawrence Douglas Andrews, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Support Mounted Electrically Interconnected Die Assembly
- Publication number 20090230528
- Publication date Sep 17, 2009
- Vertical Circuits, Inc.
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES
- Publication number 20090206458
- Publication date Aug 20, 2009
- Vertical Circuits, Inc.
- LAWRENCE DOUGLAS ANDREWS, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP SCALE STACKED DIE PACKAGE
- Publication number 20090102038
- Publication date Apr 23, 2009
- Vertical Circuits, Inc.
- SIMON J.S. MCELREA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical Interconnect Formed by Pulsed Dispense
- Publication number 20090068790
- Publication date Mar 12, 2009
- Vertical Circuits, Inc.
- Terrence Caskey
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USI...
- Publication number 20080315407
- Publication date Dec 25, 2008
- Vertical Circuits, Inc.
- Lawrence Douglas Andrews, JR.
- G01 - MEASURING TESTING
Information Patent Application
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
- Publication number 20080315434
- Publication date Dec 25, 2008
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
- Publication number 20080303131
- Publication date Dec 11, 2008
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS

LAWRENCE DOUGLAS ANDREWS, JR.

Person

Patents Grantslast 30 patents

Wafer level surface passivation of stackable integrated circuit chips

Support mounted electrically interconnected die assembly

Flat leadless packages and stacked leadless package assemblies

Wafer level surface passivation of stackable integrated circuit chips

Flat leadless packages and stacked leadless package assemblies

Patents Applicationslast 30 patents

WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

Electrically Interconnected Stacked Die Assemblies

Flat Leadless Packages and Stacked Leadless Package Assemblies

Support Mounted Electrically Interconnected Die Assembly

FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES

CHIP SCALE STACKED DIE PACKAGE

Electrical Interconnect Formed by Pulsed Dispense

THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USI...

WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES