This invention relates to electrical interconnection of integrated circuit chips and, particularly, to stackable integrated circuit devices suited for vertical interconnection. [0003] Interconnection of die with one another in a stack of die (“die-to-die”) or of a die or a die stack with a substrate (“die-to-substrate”) presents a number of challenges. For example, the integrated circuitry is situated on an “active side” of the die, and exposed pads are situated on the active side of the die for electrical interconnection with other die or with a substrate. When die are stacked, one die in the stack may obscure the pads on another die, making them inaccessible for interconnection, particularly where die having the same or similar dimensions are stacked one over another.
Various kinds of die interconnection have been proposed, including among others flip-chip interconnect, wire bond interconnect, and tab bond interconnect.
Where wire bond interconnect is employed in a stacked die assembly, the wire bonds may be formed to connect pads on the active side of a first die before an additional die is stacked over it. A spacer is typically provided upon the active side of the first die, to prevent interference by the second die with the wire loops on the first die.
Approaches to vertical interconnection of die, other than by wire bonds, bumps, or tabs are described, for example, in U.S. Pat. No. 5,675,180 and its progeny; and, for example, in U.S. Pat. No. 7,215,018 and, for example, in U.S. application Ser. No. 11/097,829.
Particularly, for example, U.S. application Ser. No. 11/097,829 describes “off-die” interconnection, employing interconnection terminals electrically connected to peripheral sites on the die and projecting beyond the die edge; interconnection of the die is made by electrically conductive polymer elements into which the projecting parts of the interconnection terminals extend.
Some die as provided have die pads along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows near the center of the die, and these may be referred to as center pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the edges of the die.
In a general aspect the invention features a stackable integrated circuit device, including an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die and a back side edge at the conjunction of back side of the die and the sidewall; and a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends onto the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends onto the back side of the die.
In some embodiments the die further includes a trace at the back side of the die, and in some such embodiments the backside trace extends over the back side edge.
In some embodiments the die has a chamfered edge at the conjunction of the front side of the die and a sidewall of the die; the conductive trace extends over the chamfer at the chamfered edge of the die and in some embodiments the conductive trace further extends over the sidewall.
In some embodiments the die further includes a back edge chamfer at the conjunction of the back side of the die and a sidewall of the die; and in some such embodiments the conductive trace extends over the back edge chamfer. In some such embodiments the die further includes a conductive trace at the back side of the die, and in some such embodiments the backside trace extends over the back edge chamfer.
In some embodiments the die includes both a front edge chamfer and a back edge chamfer at one of more of the sidewalls, and a conductive trace which is electrically connected to an interconnect pad extends over the front edge chamfer, the sidewall, the back edge chamfer and the die backside.
In some embodiments the die further includes a dielectric between the conductive trace and the chamfer; in some embodiments the die further includes a dielectric between the conductive trace and the sidewall. In some embodiments the portion of the conductive trace over the chamfer and the conductive trace over the sidewall comprise a different material; in other embodiments the portion of the conductive trace over the chamfer and the conductive trace over the sidewall comprise a similar material, or the same material.
In some embodiments the interconnect pad is one of a row of pads arranged near a centerline of the die; in other embodiments the interconnect pad is one of a row of pads arranged near an edge of the die. In some such embodiments the conductive trace extends to a chamfer at a die edge that is parallel to the row of pads; in some embodiments the conductive trace extends to a chamfer at a die edge other than a die edge that is parallel to the row of pads.
In another aspect the invention features a test socket for testing a stackable integrated circuit device as described above, including an electrically insulative base and electrically conductive contacts, each arranged to make electrical contact with a portion of the conductive trace at the chamfer, the contacts being connected to test circuitry.
In another aspect the invention features a method for testing a stackable integrated circuit device as described above, by providing a test socket as described above; moving the device toward the test socket so that the contacts make electrical contact with respective traces at the chamfer; and activating the test circuitry.
In another aspect the invention features a method for making a stackable integrated circuit device, by: providing a wafer including a plurality of semiconductor die each having edges bounded by saw streets and each having an interconnect pad on an active (front) side; forming a trench in the street, the trench defining die edges and die sidewalls; and forming an electrically conductive trace that is electrically connected to the pad and that extends to one of the edges.
In some embodiments the trench has a generally rectangular sectional profile, so that the resulting die sidewalls are generally perpendicular to the plane of the die front side (the inside angle formed at the conjunction of the die front side and the resulting sidewalls is about 90°); in other embodiments the trench has a generally trapezoidal sectional profile (with the longer parallel side at the die front side), so that the inside angle formed at the conjunction of the die front side and the resulting sidewalls is greater than 90°.
In some embodiments the electrically conductive trace is formed to extend over the edge, and in some such embodiments the electrically conductive trace is formed to extend over the edge and onto the die sidewall.
In some embodiments the method further includes forming an electrically conductive sidewall trace that is electrically connected to the conductive trace over the edge and that extends over the sidewall.
In another aspect the invention features a method for making a stackable integrated circuit device, by: providing a wafer including a plurality of semiconductor die each having edges bounded by saw streets and each having an interconnect pad on an active (front) side; forming a chamfer at each die edge; forming an electrically conductive trace that is electrically connected to the pad and that extends over one of the chamfers; and cutting the wafer to form a sidewall and to singulate the die. In some embodiments the method further includes forming an electrically conductive sidewall trace that is electrically connected to the conductive trace over the chamfer and that extends over the sidewall.
In another aspect the invention features an assembly including a stack of devices as described above, interconnected die-to-die by a conductive element that is electrically connected to the conductive trace at the chamfer and/or at the sidewall on at least two of the stacked die.
In another aspect the invention features an assembly including a device or a stack of devices as described above, interconnected to underlying circuitry (for example in a substrate or a circuit board) by a conductive element that is electrically connected to the conductive trace at the chamfer and/or at the sidewall on the die or on at least one of the stacked die.
The assemblies according to the invention can be used for building computers, telecommunications equipment, and consumer and industrial electronics devices.
The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs. Also for clarity of presentation certain features are not shown in the FIGs., where not necessary for an understanding of the invention. For example, details of the circuitry within the die are omitted.
Turning now to
Grooves are then formed in the saw streets, as shown for example in
The grooves may be formed by cutting, using for example a saw or grinding tool, or for example using a laser. Where the grooves are cut, more than one pass of the cutting tool may be employed. Or, the grooves may be formed by chemical etching, for example.
In a subsequent procedure a dielectric cap is formed in the grooves, with a result as shown for example in
The cap may be formed as a patterned layer of dielectric cap material. It may be formed by deposition and patterned removal (for example, by etch or by laser ablation), or by a patterned deposition (for example by direct write or print), or by a combination of patterned deposition and etch. Suitable materials for the dielectric cap material include, for example, a polymer that may be deposited or coated in a liquid phase, such as for example a polyimide/BT/epoxy/LCP that may or may not be directly photoimageable; a polymer that may be deposited in vapor phase, such as a parylene; or a liquid phase chemically deposited glass such as a sol-gel silica, for example.
In a subsequent procedure patterned electrically conductive traces are formed, contacting the interconnect pads 14, 16 and extending into the capped grooves, with a result as shown for example in
The conductive traces may be formed of any of a variety of electrically conductive materials, including metals and metal alloys, conductive inks, and conductive epoxies, for example. The conductive traces may be formed by any of a variety of techniques, selected as appropriate according to the material. Metal traces (gold, aluminum, copper) can be formed by applying a metal film (for example by sputtering or evaporative deposition) or metallization such as a laminate foil, or by sputtering or by plating or by a combination of sputtering and plating, and then pattering in a mask-and-etch process, for example. Electrically conductive fluids (including for example nanoparticle conductive inks) may be printed, for example by screen printing or stencil printing or by deposition from a jet or from an array of jets; or may be applied by direct transfer using a patterned stamp; or may be written, for example. Conductive epoxies or pastes, such as epoxies filled with metal particles (such as gold or silver, for example), may be dispensed, for example. The material for the traces may be a curable material; in such embodiments the curable material may be electrically conductive in the uncured condition, or only when cured, or in both the uncured and the cured condition.
In a subsequent dicing procedure the die are singulated from the wafer, with a result as shown in
In a subsequent procedure an electrically insulative sidewall cap is formed, with a result as shown in
A construct as in
The construct may be further provided with a conductive trace extending over the sidewalls.
In a subsequent procedure patterned sidewall electrically conductive traces are formed, with a result as shown in
The sidewall traces may be formed of any of the various materials, and by any of the various processes, that are used for the front side traces running from the pads to the groove. The sidewall traces may be of the same material as, or a different material from that of the front side traces, and may or may be formed using the same or a different procedure. The materials and the procedures should be selected to ensure good electrical connection between the front side traces and the sidewall traces.
As noted previously, the wafer may be thinned by backgrinding at an earlier stage in the process and, particularly, at a stage prior to dicing. Or, thinning may be carried out following the dicing procedure. If a dice-before-grind sequence is followed, it may optionally be preferable to thin prior to formation of the of the sidewall traces, to avoid damage to traces that might result from grinding.
The chamfer configuration can provide for shallower angles for wraparound of the conductive material at the die edge. Moreover, the surface of the chamfer is visible both in a view of the front side of the die and in a view of the sidewall of the die. This can provide for improved deposition of materials both on the front and on the sidewall of the die, during formation for example of the front traces and the sidewall traces.
Additionally, wraparound conductive traces are subject to stress where they are constructed over edges formed at surfaces that meet at a sharp angle. The stress can be reduced (for example where the trace is made using a conductive epoxy) where the surfaces meet at a shallower angle, and the chamfer provides for a shallower angle.
Optionally, a dielectric material may be applied to one or more surfaces of the resulting die, for mechanical protection and to maintain electrical isolation where required. A conformal coating may be applied, for example as described in U.S. application Ser. No. 11/016,558, which is hereby incorporated by reference; optionally the coating may cover all the surfaces of the die, with openings formed over areas of the conductive traces where electrical interconnection (or electrical contact for testing the die) is required.
The resulting die, provided with interconnect on a chamfered edge, may be readily tested using a test socket having contacts configured to contact the angled portions of the respective traces. Such a test socket, and use of it, is shown diagrammatically in
Two or more of such die may be stacked one over another, with a suitable dielectric between adjacent die (or a dielectric coating on at least one of the adjacent die surfaces); and the die may be readily interconnected (die-to-die, die-to-substrate; die stack-to-substrate) by forming interconnects directly on the traces, either at the vertical sidewalls or at the chamfer or at both the sidewalls and the chamfer.
The wraparound conductive traces may additionally be extended to and around the backside edges of the die.
A two-die stack including a die stacked over a construct as in
In the embodiments illustrated above the edge is chamfered at the conjunction of the front side of the die and the die sidewall. In other embodiments the die edge is not chamfered. Two such embodiments are shown by way of example in
Referring to
The trenches may be formed by cutting, using for example a saw or grinding tool, or for example using a laser. Where the grooves are cut, more than one pass of the cutting tool may be employed. Or, the trenches may be formed by chemical etching, for example.
In a later procedure a dielectric cap is formed in the trenches, with a result as shown for example in
The cap may be formed as a patterned layer of dielectric cap material. It may be formed by deposition and patterned removal (for example, by etch or by laser ablation), or by a patterned deposition (for example by direct write or print), or by a combination of patterned deposition and etch. Suitable materials for the dielectric cap material include, for example, a polymer that may be deposited or coated in a liquid phase, such as for example a polyimide/BT/epoxy/LCP that may or may not be directly photoimageable; a polymer that may be deposited in vapor phase, such as a parylene; or a liquid phase chemically deposited glass such as a sol-gel silica, for example.
In a subsequent procedure patterned electrically conductive traces are formed, contacting the interconnect pads 14,16 and extending into the capped trenches, with a result as shown for example in
The traces may end at or near the die edge, or may be formed to a small distance over the die edge, or (as shown in this example) may be formed well into the trench, onto the capped die sidewalls.
The conductive traces may be formed of any of a variety of electrically conductive materials, including metals and metal alloys, conductive inks, and conductive epoxies, for example. The conductive traces may be formed by any of a variety of techniques, selected as appropriate according to the material. Metal traces (gold, aluminum, copper) can be formed by applying a metal film (for example by sputtering or evaporative deposition) or metallization such as a laminate foil, or by sputtering or by plating or by a combination of sputtering and plating, and then pattering in a mask-and-etch process, for example. Electrically conductive fluids (including for example nanoparticle conductive inks) may be printed, for example by screen printing or stencil printing or by deposition from a jet or from an array of jets; or may be applied by direct transfer using a patterned stamp; or may be written, for example. Conductive epoxies or pastes, such as epoxies filled with metal particles (such as gold or silver, for example), may be dispensed, for example. The material for the traces may be a curable material; in such embodiments the curable material may be electrically conductive in the uncured condition, or only when cured, or in both the uncured and the cured condition.
The example shown in
In a later procedure a dielectric cap is formed in the trenches, with a result as shown for example in
In a subsequent procedure patterned electrically conductive traces are formed, contacting the interconnect pads 14, 16 and extending into the capped trenches, with a result as shown for example in
The traces may end at or near the die edge, or may be formed to a small distance over the die edge, or (as shown in this example) may be formed well into the trench, onto the capped die sidewalls.
For example, a peripheral pad die may be treated as described and shown for a center pad die. Because the pads are nearer the edges of the active region of the die (and, accordingly, nearer the saw streets), the distance between the front traces and the grooves will be shorter on a peripheral pad die than on a center pad die.
And, for example, the front traces need not be oriented perpendicularly to the groove, nor need the traces follow a straight path or the shortest path from the pads to the grooves. Moreover, the traces from any particular pad may be routed to the groove at an edge (the third or the fourth edge) other than a groove that runs parallel to the rows of pads. Not all the pads on a given die need be provided with conductive traces.
All patents and patent applications referred to herein are hereby incorporated herein by reference.
This application claims priority in part from L. D. Andrews, Jr. U.S. Provisional Application No. 60/945,274, titled “Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication”, which was filed Jun. 20, 2007, and which is hereby incorporated by reference herein.
Number | Date | Country | |
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60945274 | Jun 2007 | US |