Leon Sigal

Person

Denver, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical color decomposition of library cells with boundary-awa...
- Patent number 12,112,114
- Issue date Oct 8, 2024
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region-based power grid generation through modification of an initi...
- Patent number 11,916,384
- Issue date Feb 27, 2024
- International Business Machines Corporation
- David Wolpert
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Hierarchical color decomposition of process layers with shape and o...
- Patent number 11,822,867
- Issue date Nov 21, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch-up avoidance for sea-of-gates
- Patent number 11,663,391
- Issue date May 30, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible constraint-based logic cell placement
- Patent number 11,106,850
- Issue date Aug 31, 2021
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing and simulating library gates to enable identificatio...
- Patent number 11,074,391
- Issue date Jul 27, 2021
- International Business Machines Corporation
- Leon Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early analysis and mitigation of self-heating in design flows
- Patent number 9,990,454
- Issue date Jun 5, 2018
- International Business Machines Corporation
- Nagashyamala R. Dhanwada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for an efficient modeling of the impact of device-level self...
- Patent number 9,552,455
- Issue date Jan 24, 2017
- GLOBALFOUNDRIES INC.
- Daniel J. Poindexter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying and mitigating electromigration failures in signal nets...
- Patent number 9,104,832
- Issue date Aug 11, 2015
- International Business Machines Corporation
- John E. Barwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power grid generation through modification of an initial power grid...
- Patent number 8,914,765
- Issue date Dec 16, 2014
- International Business Machines Corporation
- Leon J. Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for hardening latches in SOI CMOS devices
- Patent number 8,354,858
- Issue date Jan 15, 2013
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LSSD compatibility for GSD unified global clock buffers
- Patent number 8,117,579
- Issue date Feb 14, 2012
- International Business Machines Corporation
- James Douglas Warnock
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for hardening latches in SOI CMOS devices
- Patent number 7,888,959
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power multi-output local clock buffer
- Patent number 7,589,565
- Issue date Sep 15, 2009
- International Business Machines Corporation
- Leon J. Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Independent migration of hierarchical designs with methods of findi...
- Patent number 7,568,173
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Veit Gernhoefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical scalable high resolution digital programmable delay ci...
- Patent number 7,456,671
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Charlie C. Hwang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for topology selection to minimize leakage power...
- Patent number 7,100,144
- Issue date Aug 29, 2006
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated programmable process and method for the improvement of el...
- Patent number 6,629,298
- Issue date Sep 30, 2003
- International Business Machines Corporation
- Peter J. Camporese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital circuit noise margin improvement
- Patent number 5,910,730
- Issue date Jun 8, 1999
- International Business Machines Corporation
- Leon Jacob Sigal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel calculation of exponent and sticky bit during normalization
- Patent number 5,757,682
- Issue date May 26, 1998
- International Business Machines Corporation
- Eric Mark Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel calculation of exponent and sticky bit during normalization
- Patent number 5,742,536
- Issue date Apr 21, 1998
- International Business Machines Corporation
- Eric Mark Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel calculation of exponent and sticky bit during normalization
- Patent number 5,742,535
- Issue date Apr 21, 1998
- International Business Machines Corporation
- Eric Mark Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel calculation of exponent and sticky bit during normalization
- Patent number 5,627,774
- Issue date May 6, 1997
- International Business Machines Corporation
- Eric M. Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic and preset static multiplexer in front of latch circuit for...
- Patent number 5,543,731
- Issue date Aug 6, 1996
- International Business Machines Corporation
- Leon J. Sigal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two-phase overlapping clocking technique for digital dynamic circuits
- Patent number 5,504,441
- Issue date Apr 2, 1996
- International Business Machines Corporation
- Leon J. Sigal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Polygon span interpolator with main memory Z buffer
- Patent number 5,493,644
- Issue date Feb 20, 1996
- Hewlett-Packard Company
- Larry J. Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VLSI clocking system using both overlapping and non-overlapping clocks
- Patent number 5,124,572
- Issue date Jun 23, 1992
- Hewlett-Packard Co.
- Russell W. Mason
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BACKSIDE SELF ALIGNED SKIP VIA
- Publication number 20240371729
- Publication date Nov 7, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS
- Publication number 20240371728
- Publication date Nov 7, 2024
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE GATE VIA STRUCTURE USING SELF-ALIGNED SCHEME
- Publication number 20240297098
- Publication date Sep 5, 2024
- International Business Machines Corporation
- Tsung-Sheng Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CELL-BASED SIGNAL CONNECTIVITY BETWEEN WAFER FRONTSIDE AND BACKSIDE
- Publication number 20240220696
- Publication date Jul 4, 2024
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ALIGNED BACKSIDE GATE CONTACTS
- Publication number 20240203792
- Publication date Jun 20, 2024
- International Business Machines Corporation
- Tsung-Sheng Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHARED SOURCE/DRAIN CONTACT FOR STACKED FIELD-EFFECT TRANSISTOR
- Publication number 20240170532
- Publication date May 23, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TI...
- Publication number 20240162895
- Publication date May 16, 2024
- International Business Machines Corporation
- BLAINE JEFFREY GROSS
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BACKSIDE SKIP-LEVEL THROUGH VIA FOR BACKSIDE SIGNAL LINE CONNECTION
- Publication number 20240162118
- Publication date May 16, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CELL OPTIMIZATION THROUGH SOURCE RESISTANCE IMPROVEMENT
- Publication number 20230317610
- Publication date Oct 5, 2023
- International Business Machines Corporation
- David WOLPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE DESIGN MITIGATING LATCH-UP
- Publication number 20230307363
- Publication date Sep 28, 2023
- International Business Machines Corporation
- David WOLPERT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GENERATING A POWER DELIVERY NETWORK BASED ON THE ROUTING OF SIGNAL...
- Publication number 20230306176
- Publication date Sep 28, 2023
- International Business Machines Corporation
- David WOLPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION-BASED POWER GRID GENERATION THROUGH MODIFICATION OF AN INITI...
- Publication number 20230090855
- Publication date Mar 23, 2023
- International Business Machines Corporation
- David Wolpert
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
LATCH-UP AVOIDANCE FOR SEA-OF-GATES
- Publication number 20230062945
- Publication date Mar 2, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL COLOR DECOMPOSITION OF PROCESS LAYERS WITH SHAPE AND O...
- Publication number 20230050539
- Publication date Feb 16, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL COLOR DECOMPOSITION OF LIBRARY CELLS WITH BOUNDARY-AWA...
- Publication number 20230050432
- Publication date Feb 16, 2023
- International Business Machines Corporation
- David Wolpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CONSTRAINT-BASED LOGIC CELL PLACEMENT
- Publication number 20210064716
- Publication date Mar 4, 2021
- International Business Machines Corporation
- David WOLPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZING AND SIMULATING LIBRARY GATES TO ENABLE IDENTIFICATIO...
- Publication number 20200233933
- Publication date Jul 23, 2020
- International Business Machines Corporation
- Leon Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY ANALYSIS AND MITIGATION OF SELF-HEATING IN DESIGN FLOWS
- Publication number 20170351785
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Nagashyamala R. Dhanwada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for an Efficient Modeling of the Impact of Device-Level Self...
- Publication number 20160224717
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Daniel J. Poindexter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS...
- Publication number 20150205906
- Publication date Jul 23, 2015
- International Buiness Machines Corporation
- John E. Barwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GRID DESIGN FOR INTEGRATED CIRCUITS
- Publication number 20140201695
- Publication date Jul 17, 2014
- International Business Machines Corporation
- Leon J. Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
- Publication number 20110102042
- Publication date May 5, 2011
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LSSD compatibility for GSD unified global clock buffers
- Publication number 20090199036
- Publication date Aug 6, 2009
- James D. Warnock
- G01 - MEASURING TESTING
Information Patent Application
LOW-POWER MULTI-OUTPUT LOCAL CLOCK BUFFER
- Publication number 20090199038
- Publication date Aug 6, 2009
- Leon J. Sigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
- Publication number 20090134925
- Publication date May 28, 2009
- International Business Machines Corporation
- Ethan H. Cannon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDI...
- Publication number 20080313581
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Veit Gernhoefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical Scalable High Resolution Digital Programmable Delay Ci...
- Publication number 20080169857
- Publication date Jul 17, 2008
- International Business Machines Corporation
- Charlie C Hwang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for topology selection to minimize leakage power...
- Publication number 20050125761
- Publication date Jun 9, 2005
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floating point bypass register to resolve data dependencies in pipe...
- Publication number 20040143613
- Publication date Jul 22, 2004
- International Business Machines Corporation
- Rainer Clemen
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Hierarchical color decomposition of library cells with boundary-awa...

Region-based power grid generation through modification of an initi...

Hierarchical color decomposition of process layers with shape and o...

Latch-up avoidance for sea-of-gates

Flexible constraint-based logic cell placement

Characterizing and simulating library gates to enable identificatio...

Early analysis and mitigation of self-heating in design flows

Method for an efficient modeling of the impact of device-level self...

Identifying and mitigating electromigration failures in signal nets...

Power grid generation through modification of an initial power grid...

Apparatus and method for hardening latches in SOI CMOS devices

LSSD compatibility for GSD unified global clock buffers

Apparatus and method for hardening latches in SOI CMOS devices

Low-power multi-output local clock buffer

Independent migration of hierarchical designs with methods of findi...

Hierarchical scalable high resolution digital programmable delay ci...

System and method for topology selection to minimize leakage power...

Automated programmable process and method for the improvement of el...

Digital circuit noise margin improvement

Parallel calculation of exponent and sticky bit during normalization

Parallel calculation of exponent and sticky bit during normalization

Parallel calculation of exponent and sticky bit during normalization

Parallel calculation of exponent and sticky bit during normalization

Dynamic and preset static multiplexer in front of latch circuit for...

Two-phase overlapping clocking technique for digital dynamic circuits

Polygon span interpolator with main memory Z buffer

VLSI clocking system using both overlapping and non-overlapping clocks

Patents Applicationslast 30 patents

BACKSIDE SELF ALIGNED SKIP VIA

BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS

BACKSIDE GATE VIA STRUCTURE USING SELF-ALIGNED SCHEME

CELL-BASED SIGNAL CONNECTIVITY BETWEEN WAFER FRONTSIDE AND BACKSIDE

SELF-ALIGNED BACKSIDE GATE CONTACTS

SHARED SOURCE/DRAIN CONTACT FOR STACKED FIELD-EFFECT TRANSISTOR

COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TI...

BACKSIDE SKIP-LEVEL THROUGH VIA FOR BACKSIDE SIGNAL LINE CONNECTION

CELL OPTIMIZATION THROUGH SOURCE RESISTANCE IMPROVEMENT

SEMICONDUCTOR DEVICE DESIGN MITIGATING LATCH-UP

GENERATING A POWER DELIVERY NETWORK BASED ON THE ROUTING OF SIGNAL...

REGION-BASED POWER GRID GENERATION THROUGH MODIFICATION OF AN INITI...

LATCH-UP AVOIDANCE FOR SEA-OF-GATES

HIERARCHICAL COLOR DECOMPOSITION OF PROCESS LAYERS WITH SHAPE AND O...

HIERARCHICAL COLOR DECOMPOSITION OF LIBRARY CELLS WITH BOUNDARY-AWA...

FLEXIBLE CONSTRAINT-BASED LOGIC CELL PLACEMENT

CHARACTERIZING AND SIMULATING LIBRARY GATES TO ENABLE IDENTIFICATIO...

EARLY ANALYSIS AND MITIGATION OF SELF-HEATING IN DESIGN FLOWS

Method for an Efficient Modeling of the Impact of Device-Level Self...

IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS...

POWER GRID DESIGN FOR INTEGRATED CIRCUITS

APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

LSSD compatibility for GSD unified global clock buffers

LOW-POWER MULTI-OUTPUT LOCAL CLOCK BUFFER

APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDI...

Hierarchical Scalable High Resolution Digital Programmable Delay Ci...

System and method for topology selection to minimize leakage power...

Floating point bypass register to resolve data dependencies in pipe...