Leopoldo D. Yau

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process for forming a thin oxide layer
- Patent number RE38674
- Issue date Dec 21, 2004
- Intel Corporation
- Robert S. K. Chau
- 438 - Semiconductor device manufacturing: process
Information Patent Grant
Transistor with ultra shallow tip and method of fabrication
- Patent number 6,326,664
- Issue date Dec 4, 2001
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with low resistance tip and method of fabrication in a C...
- Patent number 6,165,826
- Issue date Dec 26, 2000
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capping layer in interconnect system and method for bonding the cap...
- Patent number 5,863,832
- Issue date Jan 26, 1999
- Intel Corporation
- Brian Doyle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated dual layer emitter mask and emitter trench for BiCMOS pr...
- Patent number 5,856,697
- Issue date Jan 5, 1999
- Intel Corporation
- Stephen Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of frabricating a MOS transistor having a composite gate ele...
- Patent number 5,783,478
- Issue date Jul 21, 1998
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with ultra shallow tip and method of fabrication
- Patent number 5,710,450
- Issue date Jan 20, 1998
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistor having a composite gate electrode and method of fabr...
- Patent number 5,625,217
- Issue date Apr 29, 1997
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making emitter trench BiCMOS using integrated dual layer...
- Patent number 5,488,003
- Issue date Jan 30, 1996
- Intel Corporation
- Stephen Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inverted spacer transistor
- Patent number 5,434,093
- Issue date Jul 18, 1995
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a thin oxide layer
- Patent number 5,244,843
- Issue date Sep 14, 1993
- Intel Corporation
- Robert S. K. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of interpoly dielctric for EPROM-related technologies
- Patent number 5,104,819
- Issue date Apr 14, 1992
- Intel Corporation
- Philip E. Freiberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical contact apparatus for use with plasma or glow discharge...
- Patent number 4,917,044
- Issue date Apr 17, 1990
- Intel Corporation
- Leopoldo D. Yau
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Pulsed dual radio frequency CVD process
- Patent number 4,837,185
- Issue date Jun 6, 1989
- Intel Corporation
- Leopoldo D. Yau
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Plasma enhanced chemical vapor deposited vertical silicon nitride r...
- Patent number 4,786,612
- Issue date Nov 22, 1988
- Intel Corporation
- Leopoldo D. Yau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a silicon nitride resistor using plasma enhanced c...
- Patent number 4,755,480
- Issue date Jul 5, 1988
- Intel Corporation
- Leopoldo D. Yau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern delineation of vertical load resistor
- Patent number 4,690,728
- Issue date Sep 1, 1987
- Intel Corporation
- Chi-Hwa Tsang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS rear end processing
- Patent number 4,620,986
- Issue date Nov 4, 1986
- Intel Corporation
- Leopoldo D. Yau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS rear end processing
- Patent number 4,587,138
- Issue date May 6, 1986
- Intel Corporation
- Leopoldo D. Yau
- H01 - BASIC ELECTRIC ELEMENTS

Leopoldo D. Yau

Person

Patents Grantslast 30 patents

Process for forming a thin oxide layer

Transistor with ultra shallow tip and method of fabrication

Transistor with low resistance tip and method of fabrication in a C...

Capping layer in interconnect system and method for bonding the cap...

Integrated dual layer emitter mask and emitter trench for BiCMOS pr...

Method of frabricating a MOS transistor having a composite gate ele...

Transistor with ultra shallow tip and method of fabrication

MOS transistor having a composite gate electrode and method of fabr...

Method of making emitter trench BiCMOS using integrated dual layer...

Inverted spacer transistor

Process for forming a thin oxide layer

Fabrication of interpoly dielctric for EPROM-related technologies

Electrical contact apparatus for use with plasma or glow discharge...

Pulsed dual radio frequency CVD process

Plasma enhanced chemical vapor deposited vertical silicon nitride r...

Method of making a silicon nitride resistor using plasma enhanced c...

Pattern delineation of vertical load resistor

MOS rear end processing

MOS rear end processing