Lily P. Looi

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
System, apparatus and method for controlling a processor based on e...
- Patent number 11,029,744
- Issue date Jun 8, 2021
- Intel Corporation
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast page fault handling process implemented on persistent memory
- Patent number 10,949,356
- Issue date Mar 16, 2021
- Intel Corporation
- James A. Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power control techniques for integrated PCIe controllers
- Patent number 10,496,152
- Issue date Dec 3, 2019
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Throttling integrated link
- Patent number 10,241,952
- Issue date Mar 26, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device power management state transition latency advertisement for...
- Patent number 9,952,644
- Issue date Apr 24, 2018
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device power management state transition latency advertisement for...
- Patent number 9,952,643
- Issue date Apr 24, 2018
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for single-ended communication of tran...
- Patent number 9,910,814
- Issue date Mar 6, 2018
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for enabling platform power states
- Patent number 9,537,665
- Issue date Jan 3, 2017
- Intel Corporation
- Selim Bilgin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Throttling integrated link
- Patent number 9,146,610
- Issue date Sep 29, 2015
- Intel Corporation
- Ravi Rajwar
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Throttling integrated link
- Patent number 9,110,666
- Issue date Aug 18, 2015
- Intel Corporation
- Ravi Rajwar
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrating intellectual property (IP) blocks into a processor
- Patent number 9,021,156
- Issue date Apr 28, 2015
- Prashanth Nimmala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integration of processor and input/output hub
- Patent number 8,850,250
- Issue date Sep 30, 2014
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic and idle power reduction sequence using recombinant clock a...
- Patent number 8,782,456
- Issue date Jul 15, 2014
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for enabling platform power states
- Patent number 8,539,260
- Issue date Sep 17, 2013
- Intel Corporation
- Selim Bilgin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power measurement techniques of a system-on-chip (SOC)
- Patent number 8,275,560
- Issue date Sep 25, 2012
- Intel Corporation
- Sivakumar Radhakrishnan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for reducing memory latency in a cache coheren...
- Patent number 7,996,625
- Issue date Aug 9, 2011
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable protocol to support coherent and non-coherent transact...
- Patent number 7,617,329
- Issue date Nov 10, 2009
- Intel Corporation
- Tuan M. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preselecting E/M line replacement technique for a snoop filter
- Patent number 7,383,398
- Issue date Jun 3, 2008
- Intel Corporation
- Lily P Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to enable transparent memory hot plug...
- Patent number 7,376,775
- Issue date May 20, 2008
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing memory latency in a cache coheren...
- Patent number 7,234,029
- Issue date Jun 19, 2007
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling explicit writeback in a cache coherent multi...
- Patent number 7,167,957
- Issue date Jan 23, 2007
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pipelining ordered input/output transactio...
- Patent number 7,124,252
- Issue date Oct 17, 2006
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop filter bypass
- Patent number 7,093,079
- Issue date Aug 15, 2006
- Intel Corporation
- Tuan M. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling I/O transactions with known transaction leng...
- Patent number 6,976,129
- Issue date Dec 13, 2005
- Intel Corporation
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing transaction requests in a multi-n...
- Patent number 6,971,098
- Issue date Nov 29, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for initiating an implicit write-back in response to a re...
- Patent number 6,859,864
- Issue date Feb 22, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling explicit writeback in a cache coherent multi...
- Patent number 6,842,830
- Issue date Jan 11, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for centralized snoop filtering
- Patent number 6,810,467
- Issue date Oct 26, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for invalidating a cache line without data ret...
- Patent number 6,772,298
- Issue date Aug 3, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling conflicts in a multi-node computer architecture
- Patent number 6,622,215
- Issue date Sep 16, 2003
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FAST PAGE FAULT HANDLING PROCESS IMPLEMENTED ON PERSISTENT MEMORY
- Publication number 20190303300
- Publication date Oct 3, 2019
- Intel Corporation
- James A. BOYD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Controlling A Processor Based On E...
- Publication number 20190204893
- Publication date Jul 4, 2019
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...
- Publication number 20160116959
- Publication date Apr 28, 2016
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...
- Publication number 20160110309
- Publication date Apr 21, 2016
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROTTLING INTEGRATED LINK
- Publication number 20160085711
- Publication date Mar 24, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...
- Publication number 20150269109
- Publication date Sep 24, 2015
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS
- Publication number 20150095687
- Publication date Apr 2, 2015
- BRYAN L. SPRY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...
- Publication number 20140281639
- Publication date Sep 18, 2014
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR ENABLING PLATFORM POWER STATES
- Publication number 20130336336
- Publication date Dec 19, 2013
- Selim Bilgin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrating Intellectual Property (IP) Blocks Into A Processor
- Publication number 20130054845
- Publication date Feb 28, 2013
- Prashanth Nimmala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Throttling Integrated Link
- Publication number 20120079159
- Publication date Mar 29, 2012
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB
- Publication number 20110296216
- Publication date Dec 1, 2011
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK A...
- Publication number 20110296222
- Publication date Dec 1, 2011
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for enabling platform power states
- Publication number 20110246798
- Publication date Oct 6, 2011
- Selim Bilgin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preselecting E/M line replacement technique for a snoop filter
- Publication number 20070239941
- Publication date Oct 11, 2007
- Lily P. Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Way hint line replacement algorithm for a snoop filter
- Publication number 20070233965
- Publication date Oct 4, 2007
- Kai Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing memory latency in a cache coheren...
- Publication number 20070204111
- Publication date Aug 30, 2007
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20060106993
- Publication date May 18, 2006
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to enable transparent memory hot plug/remove
- Publication number 20050149314
- Publication date Jul 7, 2005
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20040268061
- Publication date Dec 30, 2004
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable protocol to support coherent and non-coherent transact...
- Publication number 20040139234
- Publication date Jul 15, 2004
- Tuan M. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to broadcast transactions to multiple agents in a multi-n...
- Publication number 20040128351
- Publication date Jul 1, 2004
- Intel Corporation
- Robert J. Hoogland
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Snoop filter bypass
- Publication number 20040117561
- Publication date Jun 17, 2004
- Tuan M. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling I/O transactions with known transaction leng...
- Publication number 20040064652
- Publication date Apr 1, 2004
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for initiating an implicit write-back in response to a re...
- Publication number 20030131202
- Publication date Jul 10, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for efficiently supporting the full MESI (modified, exclu...
- Publication number 20030131201
- Publication date Jul 10, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for managing transaction requests in a multi-n...
- Publication number 20030005167
- Publication date Jan 2, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20020178210
- Publication date Nov 28, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling conflicts in a multi-node computer architecture
- Publication number 20020129206
- Publication date Sep 12, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing memory latency in a cache coheren...
- Publication number 20020087811
- Publication date Jul 4, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING

Lily P. Looi

Person

Patents Grantslast 30 patents

System, apparatus and method for controlling a processor based on e...

Fast page fault handling process implemented on persistent memory

Power control techniques for integrated PCIe controllers

Throttling integrated link

Device power management state transition latency advertisement for...

Device power management state transition latency advertisement for...

Method, apparatus and system for single-ended communication of tran...

Method, apparatus, and system for enabling platform power states

Throttling integrated link

Throttling integrated link

Integrating intellectual property (IP) blocks into a processor

Integration of processor and input/output hub

Dynamic and idle power reduction sequence using recombinant clock a...

Method, apparatus, and system for enabling platform power states

Power measurement techniques of a system-on-chip (SOC)

Method and apparatus for reducing memory latency in a cache coheren...

Programmable protocol to support coherent and non-coherent transact...

Preselecting E/M line replacement technique for a snoop filter

Apparatus, system, and method to enable transparent memory hot plug...

Method and apparatus for reducing memory latency in a cache coheren...

Mechanism for handling explicit writeback in a cache coherent multi...

Method and apparatus for pipelining ordered input/output transactio...

Snoop filter bypass

Mechanism for handling I/O transactions with known transaction leng...

Method and apparatus for managing transaction requests in a multi-n...

Mechanism for initiating an implicit write-back in response to a re...

Mechanism for handling explicit writeback in a cache coherent multi...

Method and apparatus for centralized snoop filtering

Method and apparatus for invalidating a cache line without data ret...

Mechanism for handling conflicts in a multi-node computer architecture

Patents Applicationslast 30 patents

FAST PAGE FAULT HANDLING PROCESS IMPLEMENTED ON PERSISTENT MEMORY

System, Apparatus And Method For Controlling A Processor Based On E...

DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...

DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...

THROTTLING INTEGRATED LINK

METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...

POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS

DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR...

METHOD, APPARATUS, AND SYSTEM FOR ENABLING PLATFORM POWER STATES

Integrating Intellectual Property (IP) Blocks Into A Processor

Throttling Integrated Link

INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB

DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK A...

Method, apparatus, and system for enabling platform power states

Preselecting E/M line replacement technique for a snoop filter

Way hint line replacement algorithm for a snoop filter

Method and apparatus for reducing memory latency in a cache coheren...

Mechanism for handling explicit writeback in a cache coherent multi...

Apparatus and method to enable transparent memory hot plug/remove

Mechanism for handling explicit writeback in a cache coherent multi...

Programmable protocol to support coherent and non-coherent transact...

Mechanism to broadcast transactions to multiple agents in a multi-n...

Snoop filter bypass

Mechanism for handling I/O transactions with known transaction leng...

Mechanism for initiating an implicit write-back in response to a re...

Mechanism for efficiently supporting the full MESI (modified, exclu...

Method and apparatus for managing transaction requests in a multi-n...

Mechanism for handling explicit writeback in a cache coherent multi...

Mechanism for handling conflicts in a multi-node computer architecture

Method and apparatus for reducing memory latency in a cache coheren...