Loren A. Chow

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of forming hetero-layers with reduced surface roughness and...
- Patent number 9,711,591
- Issue date Jul 18, 2017
- Intel Corporation
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,617,945
- Issue date Dec 31, 2013
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,143,646
- Issue date Mar 27, 2012
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,851,781
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming buffer layer architecture on silicon and structu...
- Patent number 7,687,799
- Issue date Mar 30, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation-free InSb quantum well structure on Si using novel buff...
- Patent number 7,573,059
- Issue date Aug 11, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,494,911
- Issue date Feb 24, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V and II-VI compounds as template materials for growing germani...
- Patent number 7,202,503
- Issue date Apr 10, 2007
- Intel Corporation
- Loren Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite dielectric layers
- Patent number 6,876,081
- Issue date Apr 5, 2005
- Intel Corporation
- Loren A. Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite dielectric layers
- Patent number 6,674,146
- Issue date Jan 6, 2004
- Intel Corporation
- Loren A. Chow
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI
- Publication number 20120142166
- Publication date Jun 7, 2012
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of forming buffer layer architecture on silicon and structu...
- Publication number 20090315018
- Publication date Dec 24, 2009
- Mantu K. Hudait
- B82 - NANO-TECHNOLOGY
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20090218596
- Publication date Sep 3, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation-free InSb quantum well structure on Si using novel buff...
- Publication number 20080073639
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20080076235
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacking fault and twin blocking barrier for integrating III-V on Si
- Publication number 20080032478
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Depositing polar materials on non-polar semiconductor substrates
- Publication number 20070238281
- Publication date Oct 11, 2007
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V and II-VI compounds as template materials for growing germani...
- Publication number 20060001018
- Publication date Jan 5, 2006
- Loren Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Composite dielectric layers
- Publication number 20040046259
- Publication date Mar 11, 2004
- Loren A. Chow
- H01 - BASIC ELECTRIC ELEMENTS

Loren A. Chow

Person

Patents Grantslast 30 patents

Methods of forming hetero-layers with reduced surface roughness and...

Stacking fault and twin blocking barrier for integrating III-V on Si

Stacking fault and twin blocking barrier for integrating III-V on Si

Buffer layers for device isolation of devices grown on silicon

Methods of forming buffer layer architecture on silicon and structu...

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer layers for device isolation of devices grown on silicon

III-V and II-VI compounds as template materials for growing germani...

Composite dielectric layers

Composite dielectric layers

Patents Applicationslast 30 patents

STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI

Methods of forming buffer layer architecture on silicon and structu...

Buffer layers for device isolation of devices grown on silicon

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer layers for device isolation of devices grown on silicon

Stacking fault and twin blocking barrier for integrating III-V on Si

Depositing polar materials on non-polar semiconductor substrates

III-V and II-VI compounds as template materials for growing germani...

Composite dielectric layers