Low Siu Waf

Person

Singpore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Method for packaging circuits
- Patent number 10,811,278
- Issue date Oct 20, 2020
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for packaging circuits
- Patent number 10,453,704
- Issue date Oct 22, 2019
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for packaging circuits
- Patent number 9,484,225
- Issue date Nov 1, 2016
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged microelectronic components with terminals exposed through...
- Patent number 8,637,973
- Issue date Jan 28, 2014
- Micron Technology, Inc.
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for packaging circuits
- Patent number 8,555,495
- Issue date Oct 15, 2013
- Micron Technology, Inc.
- Yong Poo Chia
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Apparatus and method for packaging circuits
- Patent number 8,138,617
- Issue date Mar 20, 2012
- Round Rock Research, LLC
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for packaging circuits
- Patent number 8,115,306
- Issue date Feb 14, 2012
- Round Rock Research, LLC
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for packaging circuits
- Patent number 8,065,792
- Issue date Nov 29, 2011
- Micron Technology, Inc.
- Yong Poo Chia
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 8,008,126
- Issue date Aug 30, 2011
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for packaging circuits and packaged circuits
- Patent number 7,712,211
- Issue date May 11, 2010
- Micron Technology, Inc.
- Yong Poo Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 7,679,179
- Issue date Mar 16, 2010
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for packaging circuits
- Patent number 7,675,169
- Issue date Mar 9, 2010
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 7,528,477
- Issue date May 5, 2009
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating packaged die
- Patent number 7,358,154
- Issue date Apr 15, 2008
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Support elements for semiconductor devices with peripherally locate...
- Patent number 7,285,850
- Issue date Oct 23, 2007
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 7,276,387
- Issue date Oct 2, 2007
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and semiconductor device components with peri...
- Patent number 7,226,809
- Issue date Jun 5, 2007
- Micron Technology, Inc.
- Chia Yong Poo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Packaged microelectronic components
- Patent number 7,195,957
- Issue date Mar 27, 2007
- Micron Technology, Inc.
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-process semiconductor packages with leadframe grid arrays
- Patent number 7,170,161
- Issue date Jan 30, 2007
- Micron Technology, Inc.
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices including peripherally located bond pads, int...
- Patent number 7,115,984
- Issue date Oct 3, 2006
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making semiconductor packages with leadframe grid arrays
- Patent number 6,967,127
- Issue date Nov 22, 2005
- Micron Technology, Inc.
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 6,949,407
- Issue date Sep 27, 2005
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for packaging circuits
- Patent number 6,894,386
- Issue date May 17, 2005
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Castellation wafer level packaging of integrated circuit chips
- Patent number 6,855,572
- Issue date Feb 15, 2005
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-substrate microelectronic packages and methods for manufacture
- Patent number 6,841,418
- Issue date Jan 11, 2005
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages with leadframe grid arrays and components
- Patent number 6,836,008
- Issue date Dec 28, 2004
- Micron Technology, Inc.
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged microelectronic components
- Patent number 6,836,009
- Issue date Dec 28, 2004
- Micron Technology, Inc.
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and semiconductor device components with peri...
- Patent number 6,818,977
- Issue date Nov 16, 2004
- Micron Technology, Inc.
- Chia Yong Poo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus and method for leadless packaging of semiconductor devices
- Patent number 6,790,706
- Issue date Sep 14, 2004
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for leadless packaging of semiconductor devices
- Patent number 6,787,894
- Issue date Sep 7, 2004
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR PACKAGING CIRCUITS
- Publication number 20190362988
- Publication date Nov 28, 2019
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING CIRCUITS
- Publication number 20170047231
- Publication date Feb 16, 2017
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING CIRCUITS
- Publication number 20140045280
- Publication date Feb 13, 2014
- Micron Technology, Inc.
- Chia Y. Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING CIRCUITS
- Publication number 20120064697
- Publication date Mar 15, 2012
- Yong Poo Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS
- Publication number 20100146780
- Publication date Jun 17, 2010
- Yong Poo Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR PACKAGING CIRCUITS
- Publication number 20100140794
- Publication date Jun 10, 2010
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS
- Publication number 20100068851
- Publication date Mar 18, 2010
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED MICROELECTRONIC COMPONENTS
- Publication number 20080067642
- Publication date Mar 20, 2008
- Micron Technology, Inc.
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS
- Publication number 20080067675
- Publication date Mar 20, 2008
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor packages having leadframe-based connection arrays
- Publication number 20070120247
- Publication date May 31, 2007
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices including peripherally located bond pads, int...
- Publication number 20060208351
- Publication date Sep 21, 2006
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Support elements for semiconductor devices with peripherally locate...
- Publication number 20060208350
- Publication date Sep 21, 2006
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method for packaging circuits
- Publication number 20060084240
- Publication date Apr 20, 2006
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Castellation wafer level packaging of integrated circuit chips
- Publication number 20060014319
- Publication date Jan 19, 2006
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Castellation wafer level packaging of integrated circuit chips
- Publication number 20060008946
- Publication date Jan 12, 2006
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Castellation wafer level packaging of integrated circuit chips
- Publication number 20060006519
- Publication date Jan 12, 2006
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Castellation wafer level packaging of integrated circuit chips
- Publication number 20060001142
- Publication date Jan 5, 2006
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for making semiconductor packages with leadframe grid arrays
- Publication number 20050230808
- Publication date Oct 20, 2005
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS
- Publication number 20050130345
- Publication date Jun 16, 2005
- Micron Technology, Inc.
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method for packaging circuits
- Publication number 20050029668
- Publication date Feb 10, 2005
- Micron Technology, Inc.
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaged microelectronic components
- Publication number 20050026325
- Publication date Feb 3, 2005
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for packaging circuits and packaged circuits
- Publication number 20040221451
- Publication date Nov 11, 2004
- Micron Technology, Inc.
- Yong Poo Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-substrate microelectronic packages and methods for manufacture
- Publication number 20040183207
- Publication date Sep 23, 2004
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices including peripherally located bond pads, int...
- Publication number 20040124523
- Publication date Jul 1, 2004
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Castellation wafer level packaging of integrated circuit chips
- Publication number 20040043535
- Publication date Mar 4, 2004
- Boon Suan Jeung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaged microelectronic components
- Publication number 20040026773
- Publication date Feb 12, 2004
- Eng Meow Koon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices and semiconductor device components with peri...
- Publication number 20030230802
- Publication date Dec 18, 2003
- Chia Yong Poo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, ASS...
- Publication number 20030232460
- Publication date Dec 18, 2003
- Chia Yong Poo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices and semiconductor device components with peri...
- Publication number 20030232462
- Publication date Dec 18, 2003
- Chia Yong Poo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor packages with leadframe grid arrays and components an...
- Publication number 20030193091
- Publication date Oct 16, 2003
- Chan Min Yu
- H01 - BASIC ELECTRIC ELEMENTS

Low Siu Waf

Person

Patents Grantslast 30 patents

Method for packaging circuits

Method for packaging circuits

Method for packaging circuits

Packaged microelectronic components with terminals exposed through...

Method for packaging circuits

Apparatus and method for packaging circuits

Apparatus and method for packaging circuits

Method for packaging circuits

Castellation wafer level packaging of integrated circuit chips

Method for packaging circuits and packaged circuits

Castellation wafer level packaging of integrated circuit chips

Apparatus and method for packaging circuits

Castellation wafer level packaging of integrated circuit chips

Method for fabricating packaged die

Support elements for semiconductor devices with peripherally locate...

Castellation wafer level packaging of integrated circuit chips

Semiconductor devices and semiconductor device components with peri...

Packaged microelectronic components

In-process semiconductor packages with leadframe grid arrays

Semiconductor devices including peripherally located bond pads, int...

Methods for making semiconductor packages with leadframe grid arrays

Castellation wafer level packaging of integrated circuit chips

Apparatus and method for packaging circuits

Castellation wafer level packaging of integrated circuit chips

Multi-substrate microelectronic packages and methods for manufacture

Semiconductor packages with leadframe grid arrays and components

Packaged microelectronic components

Semiconductor devices and semiconductor device components with peri...

Apparatus and method for leadless packaging of semiconductor devices

Apparatus and method for leadless packaging of semiconductor devices

Patents Applicationslast 30 patents

METHOD FOR PACKAGING CIRCUITS

METHOD FOR PACKAGING CIRCUITS

METHOD FOR PACKAGING CIRCUITS

METHOD FOR PACKAGING CIRCUITS

METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS

APPARATUS AND METHOD FOR PACKAGING CIRCUITS

CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS

PACKAGED MICROELECTRONIC COMPONENTS

CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS

Semiconductor packages having leadframe-based connection arrays

Semiconductor devices including peripherally located bond pads, int...

Support elements for semiconductor devices with peripherally locate...

Apparatus and method for packaging circuits

Castellation wafer level packaging of integrated circuit chips

Castellation wafer level packaging of integrated circuit chips

Castellation wafer level packaging of integrated circuit chips

Castellation wafer level packaging of integrated circuit chips

Methods for making semiconductor packages with leadframe grid arrays

CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS

Apparatus and method for packaging circuits

Packaged microelectronic components

Method for packaging circuits and packaged circuits

Multi-substrate microelectronic packages and methods for manufacture

Semiconductor devices including peripherally located bond pads, int...

Castellation wafer level packaging of integrated circuit chips

Packaged microelectronic components

Semiconductor devices and semiconductor device components with peri...

SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, ASS...

Semiconductor devices and semiconductor device components with peri...

Semiconductor packages with leadframe grid arrays and components an...