Luca Ciccarelli

Person

Rimini, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Method of designing a high performance application specific integra...
- Patent number 8,910,103
- Issue date Dec 9, 2014
- STMicroelectronics S.R.L.
- Fabio Campi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Base cell for implementing an engineering change order (ECO)
- Patent number 8,390,330
- Issue date Mar 5, 2013
- STMicroelectronics S.R.L.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication system between a first and a second synchronous devic...
- Patent number 8,238,502
- Issue date Aug 7, 2012
- STMicroelectronics S.r.l.
- Luca Magagni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for implementing functional changes into a design layout of...
- Patent number 8,214,774
- Issue date Jul 3, 2012
- STMicroelectronics S.r.l.
- Valentina Nardone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Base cell for engineering change order (ECO) implementation
- Patent number 7,965,107
- Issue date Jun 21, 2011
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous interconnection system for 3D interchip communication
- Patent number 7,821,293
- Issue date Oct 26, 2010
- STMicroelectronics, SRL
- Alberto Fazzi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip-to-chip communication system and method
- Patent number 7,808,276
- Issue date Oct 5, 2010
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication system for connecting synchronous devices that are un...
- Patent number 7,772,888
- Issue date Aug 10, 2010
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
T-switch buffer, in particular for FPGA architectures
- Patent number 7,683,674
- Issue date Mar 23, 2010
- STMicroelectronics, SRL
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switch block and corresponding switch matrix, in particular for FPG...
- Patent number 7,463,055
- Issue date Dec 9, 2008
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switch block for FPGA architectures
- Patent number 7,463,067
- Issue date Dec 9, 2008
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for a connection block in reconfigurable gate arrays
- Patent number 7,193,437
- Issue date Mar 20, 2007
- STMicroelectronics S.r.l.
- Andrea Cappelli
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO)
- Publication number 20120001655
- Publication date Jan 5, 2012
- STMicroelectronics S.r.I.
- Luca CICCARELLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IMPLEMENTING FUNCTIONAL CHANGES INTO A DESIGN LAYOUT OF...
- Publication number 20100201400
- Publication date Aug 12, 2010
- STMicroelectronics S.r.l.
- Valentina Nardone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION
- Publication number 20100164547
- Publication date Jul 1, 2010
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC...
- Publication number 20100169857
- Publication date Jul 1, 2010
- STMicroelectronics S.r.I.
- Fabio Campi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEM FOR CONNECTING SYNCHRONOUS DEVICES THAT ARE UN...
- Publication number 20090168938
- Publication date Jul 2, 2009
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEM BETWEEN A FIRST AND A SECOND SYNCHRONOUS DEVIC...
- Publication number 20090168860
- Publication date Jul 2, 2009
- STMicroelectronics S.r.l.
- Luca Magagni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Asynchronous interconnection system for 3D interchip communication
- Publication number 20080225987
- Publication date Sep 18, 2008
- STMicroelectronics S.r.l.
- Alberto Fazzi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
T-switch buffer, in particular for FPGA architectures
- Publication number 20070279088
- Publication date Dec 6, 2007
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Chip-to-chip communication system and method
- Publication number 20070092011
- Publication date Apr 26, 2007
- Luca Ciccarelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCH BLOCK FOR FPGA ARCHITECTURES
- Publication number 20070085563
- Publication date Apr 19, 2007
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Switch block and corresponding switch matrix, in particular for FPG...
- Publication number 20060103420
- Publication date May 18, 2006
- STMicroelectronics S.r.l.
- Luca Ciccarelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Architecture for a connection block in reconfigurable gate arrays
- Publication number 20040225980
- Publication date Nov 11, 2004
- STMicroelectronics S.r.l.
- Andrea Cappelli
- H03 - BASIC ELECTRONIC CIRCUITRY

Luca Ciccarelli

Person

Patents Grantslast 30 patents

Method of designing a high performance application specific integra...

Base cell for implementing an engineering change order (ECO)

Communication system between a first and a second synchronous devic...

Method for implementing functional changes into a design layout of...

Base cell for engineering change order (ECO) implementation

Asynchronous interconnection system for 3D interchip communication

Chip-to-chip communication system and method

Communication system for connecting synchronous devices that are un...

T-switch buffer, in particular for FPGA architectures

Switch block and corresponding switch matrix, in particular for FPG...

Switch block for FPGA architectures

Architecture for a connection block in reconfigurable gate arrays

Patents Applicationslast 30 patents

BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO)

METHOD FOR IMPLEMENTING FUNCTIONAL CHANGES INTO A DESIGN LAYOUT OF...

BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION

METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC...

COMMUNICATION SYSTEM FOR CONNECTING SYNCHRONOUS DEVICES THAT ARE UN...

COMMUNICATION SYSTEM BETWEEN A FIRST AND A SECOND SYNCHRONOUS DEVIC...

Asynchronous interconnection system for 3D interchip communication

T-switch buffer, in particular for FPGA architectures

Chip-to-chip communication system and method

SWITCH BLOCK FOR FPGA ARCHITECTURES

Switch block and corresponding switch matrix, in particular for FPG...

Architecture for a connection block in reconfigurable gate arrays