Ludo Deferm

Person

Beverloo, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming a FET having L-shaped insulating spacers
- Patent number 6,380,039
- Issue date Apr 30, 2002
- Interuniversitair Microelektronica Centrum (IMEC VZW)
- Goncal Badenes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of erasing a flash EEPROM memory cell array optimized for lo...
- Patent number 6,282,124
- Issue date Aug 28, 2001
- Interuniversitair Microelektronica Centrum (IMEC, vzw)
- Jan F. Van Houdt
- G11 - INFORMATION STORAGE
Information Patent Grant
Etching process of CoSi2 layers
- Patent number 6,255,227
- Issue date Jul 3, 2001
- Interuniversitair Microelektronica Centrum
- Ricardo Alves Donaton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etching process of CoSi.sub.2 layers
- Patent number 6,153,484
- Issue date Nov 28, 2000
- IMEC vzw
- Ricardo Alves Donaton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully overlapped nitride-etch defined device and processing sequence
- Patent number 6,071,825
- Issue date Jun 6, 2000
- InterUniversitaire Microelektronica Centrum (IMEC VZW)
- Ludo Deferm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of programming a flash EEPROM memory cell array optimized fo...
- Patent number 6,044,015
- Issue date Mar 28, 2000
- IMEC vzw
- Jan F. Van Houdt
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of erasing a flash EEPROM memory cell array optimized for lo...
- Patent number 5,969,991
- Issue date Oct 19, 1999
- Interuniversitair Micro-Elektronica Centrum vzw
- Jan F. Van Houdt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FORMING A FET
- Publication number 20010012668
- Publication date Aug 9, 2001
- GONCAL BADENES
- H01 - BASIC ELECTRIC ELEMENTS

Ludo Deferm

Person

Patents Grantslast 30 patents

Method for forming a FET having L-shaped insulating spacers

Method of erasing a flash EEPROM memory cell array optimized for lo...

Etching process of CoSi2 layers

Etching process of CoSi.sub.2 layers

Fully overlapped nitride-etch defined device and processing sequence

Method of programming a flash EEPROM memory cell array optimized fo...

Method of erasing a flash EEPROM memory cell array optimized for lo...

Patents Applicationslast 30 patents

METHOD FOR FORMING A FET