Maher Amer

Person

Nepean, CA

People

Patents Grantslast 30 patents

Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 11,789,662
- Issue date Oct 17, 2023
- RAMBUS INC.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing a configurable timing control for a...
- Patent number 11,640,836
- Issue date May 2, 2023
- RAMBUS INC.
- Michael L. Takefman
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 11,422,749
- Issue date Aug 23, 2022
- RAMBUS INC.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for implementing a multi-threaded device driver i...
- Patent number 11,061,841
- Issue date Jul 13, 2021
- Rambus, Inc.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing a configurable timing control for a...
- Patent number 11,062,743
- Issue date Jul 13, 2021
- Rambus, Inc.
- Michael L. Takefman
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 10,942,682
- Issue date Mar 9, 2021
- RAMBUS INC.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 10,725,704
- Issue date Jul 28, 2020
- RAMBUS INC.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for implementing a multi-threaded device driver i...
- Patent number 10,719,466
- Issue date Jul 21, 2020
- RAMBUS INC.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing a configurable timing control for a...
- Patent number 10,580,465
- Issue date Mar 3, 2020
- Rambus Inc.
- Michael L. Takefman
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 10,168,954
- Issue date Jan 1, 2019
- Rambus Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing an address cache for memory map lea...
- Patent number 9,779,020
- Issue date Oct 3, 2017
- Diablo Technologies Inc.
- Michael L. Takefman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for unlocking additional functions of a module
- Patent number 9,575,908
- Issue date Feb 21, 2017
- Diablo Technologies Inc.
- Michael L. Takefman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for providing a command buffer in a memory system
- Patent number 9,552,175
- Issue date Jan 24, 2017
- Diablo Technologies Inc.
- Michael L. Takefman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Load reduction dual in-line memory module (LRDIMM) and method for p...
- Patent number 9,465,557
- Issue date Oct 11, 2016
- Diablo Technologies Inc.
- Maher Amer
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for offsetting the data buffer latency of a devic...
- Patent number 9,449,651
- Issue date Sep 20, 2016
- Diablo Technologies Inc.
- Michael L. Takefman
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 9,444,495
- Issue date Sep 13, 2016
- Diablo Technologies Inc.
- Michael L. Takefman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Load reduction dual in-line memory module (LRDIMM) and method for p...
- Patent number 9,015,408
- Issue date Apr 21, 2015
- Diablo Technologies, Inc.
- Maher Amer
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 8,972,805
- Issue date Mar 3, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Load reduction dual in-line memory module (LRDIMM) and method for p...
- Patent number 8,738,853
- Issue date May 27, 2014
- Diablo Technologies Inc.
- Maher Amer
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of interfacing co-processors and input/output dev...
- Patent number 8,713,379
- Issue date Apr 29, 2014
- Diablo Technologies Inc.
- Michael L. Takefman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Load reduction dual in-line memory module (LRDIMM) and method for p...
- Patent number 8,452,917
- Issue date May 28, 2013
- Diablo Technologies Inc.
- Maher Amer
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized FFT/IFFT module
- Patent number 8,107,357
- Issue date Jan 31, 2012
- Zarbana Digital Fund LLC
- Maher Amer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system and method for use in trellis-based decoding
- Patent number 7,917,835
- Issue date Mar 29, 2011
- Zarbana Digital Fund LLC
- Maher Amer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel convolutional encoder
- Patent number 7,765,457
- Issue date Jul 27, 2010
- Maher Amer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and modules for use with trellis-based decoding
- Patent number 7,623,585
- Issue date Nov 24, 2009
- Maher Amer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel scrambler/descrambler
- Patent number 7,415,112
- Issue date Aug 19, 2008
- Zarbana Digital Fund LLC
- Maher Amer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized FFT/IFFT module
- Patent number 7,333,422
- Issue date Feb 19, 2008
- Zarbana Digital Fund LLC
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel convolutional encoder
- Patent number 7,318,189
- Issue date Jan 8, 2008
- Zarbana Digital Fund LLC
- Maher Amer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory system and method for use in trellis-based decoding
- Patent number 7,185,268
- Issue date Feb 27, 2007
- Maher Amer
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20220405018
- Publication date Dec 22, 2022
- Rambus Inc.
- Michael L. TAKEFMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...
- Publication number 20210407561
- Publication date Dec 30, 2021
- Rambus Inc.
- MICHAEL L. TAKEFMAN
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20210318835
- Publication date Oct 14, 2021
- Rambus Inc.
- Michael L. TAKEFMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20210011661
- Publication date Jan 14, 2021
- Rambus Inc.
- Michael L. TAKEFMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...
- Publication number 20210004341
- Publication date Jan 7, 2021
- Rambus Inc.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...
- Publication number 20200265876
- Publication date Aug 20, 2020
- RAMBUS INC.
- MICHAEL L. TAKEFMAN
- G11 - INFORMATION STORAGE
Information Patent Application
HARDWARE BASED VIRTUAL MEMORY MANAGEMENT
- Publication number 20190303316
- Publication date Oct 3, 2019
- BioNym Consulting Inc
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20190212948
- Publication date Jul 11, 2019
- RAMBUS INC.
- Michael L. TAKEFMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...
- Publication number 20190065420
- Publication date Feb 28, 2019
- RAMBUS INC.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...
- Publication number 20190043541
- Publication date Feb 7, 2019
- RAMBUS INC.
- MICHAEL L. TAKEFMAN
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20160378404
- Publication date Dec 29, 2016
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVIC...
- Publication number 20160371204
- Publication date Dec 22, 2016
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...
- Publication number 20160041933
- Publication date Feb 11, 2016
- Diablo Technologies, Inc.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MIRRORING A VOLATILE MEMORY OF A COMPUTER SYSTEM
- Publication number 20160041917
- Publication date Feb 11, 2016
- Diablo Technologies, Inc.
- Bart Trojanowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR BOOTING FROM A NON-VOLATILE MEMORY
- Publication number 20150347151
- Publication date Dec 3, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COM...
- Publication number 20150324281
- Publication date Nov 12, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/O...
- Publication number 20150326684
- Publication date Nov 12, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...
- Publication number 20150310898
- Publication date Oct 29, 2015
- Diablo Technologies Inc.
- MICHAEL L. TAKEFMAN
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method of Interfacing Co-Processors and Input/Output Dev...
- Publication number 20150309959
- Publication date Oct 29, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Offsetting The Data Buffer Latency of a Devic...
- Publication number 20150294698
- Publication date Oct 15, 2015
- Diablo Technologies Inc.
- Michael L. Takefman
- G11 - INFORMATION STORAGE
Information Patent Application
LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...
- Publication number 20150227324
- Publication date Aug 13, 2015
- Diablo Technologies Inc.
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...
- Publication number 20140244924
- Publication date Aug 28, 2014
- Diablo Technologies Inc.
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING AN ADDRESS CACHE FOR MEMORY MAP LEA...
- Publication number 20140237157
- Publication date Aug 21, 2014
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING A COMMAND BUFFER IN A MEMORY SYSTEM
- Publication number 20140237205
- Publication date Aug 21, 2014
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR UNLOCKING ADDITIONAL FUNCTIONS OF A MODULE
- Publication number 20140237176
- Publication date Aug 21, 2014
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Interfacing Co-Processors and Input/Output Dev...
- Publication number 20140223262
- Publication date Aug 7, 2014
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...
- Publication number 20130238849
- Publication date Sep 12, 2013
- Diablo Technologies Inc.
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...
- Publication number 20120204079
- Publication date Aug 9, 2012
- Diablo Technologies Inc.
- Michael L. Takefman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...
- Publication number 20100070690
- Publication date Mar 18, 2010
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED FFT/IFFT MODULE
- Publication number 20080172436
- Publication date Jul 17, 2008
- Zarbana Digital Fund LLC
- Maher Amer
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

System and method of interfacing co-processors and input/output dev...

System and method for providing a configurable timing control for a...

System and method of interfacing co-processors and input/output dev...

System and method for implementing a multi-threaded device driver i...

System and method for providing a configurable timing control for a...

System and method of interfacing co-processors and input/output dev...

System and method of interfacing co-processors and input/output dev...

System and method for implementing a multi-threaded device driver i...

System and method for providing a configurable timing control for a...

System and method of interfacing co-processors and input/output dev...

System and method for providing an address cache for memory map lea...

System and method for unlocking additional functions of a module

System and method for providing a command buffer in a memory system

Load reduction dual in-line memory module (LRDIMM) and method for p...

System and method for offsetting the data buffer latency of a devic...

System and method of interfacing co-processors and input/output dev...

Load reduction dual in-line memory module (LRDIMM) and method for p...

System and method of interfacing co-processors and input/output dev...

Load reduction dual in-line memory module (LRDIMM) and method for p...

System and method of interfacing co-processors and input/output dev...

Load reduction dual in-line memory module (LRDIMM) and method for p...

Optimized FFT/IFFT module

Memory system and method for use in trellis-based decoding

Parallel convolutional encoder

Systems and modules for use with trellis-based decoding

Parallel scrambler/descrambler

Optimized FFT/IFFT module

Parallel convolutional encoder

Memory system and method for use in trellis-based decoding

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...

SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...

HARDWARE BASED VIRTUAL MEMORY MANAGEMENT

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...

SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVIC...

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER I...

SYSTEM AND METHOD FOR MIRRORING A VOLATILE MEMORY OF A COMPUTER SYSTEM

SYSTEM AND METHOD FOR BOOTING FROM A NON-VOLATILE MEMORY

SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COM...

SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/O...

SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A...

System and Method of Interfacing Co-Processors and Input/Output Dev...

System and Method for Offsetting The Data Buffer Latency of a Devic...

LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...

LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...

SYSTEM AND METHOD FOR PROVIDING AN ADDRESS CACHE FOR MEMORY MAP LEA...

SYSTEM AND METHOD FOR PROVIDING A COMMAND BUFFER IN A MEMORY SYSTEM

SYSTEM AND METHOD FOR UNLOCKING ADDITIONAL FUNCTIONS OF A MODULE

System and Method of Interfacing Co-Processors and Input/Output Dev...

LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEV...

LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR P...

OPTIMIZED FFT/IFFT MODULE