Majid Nemati Anaraki

Person

Irvine, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical variable code rate error correction coding
- Patent number 10,509,603
- Issue date Dec 17, 2019
- Western Digital Technologies, Inc.
- Scott Thomas Kayser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tapered variable node memory
- Patent number 10,289,348
- Issue date May 14, 2019
- Western Digital Technologies, Inc.
- Jake Bear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-binary LDPC decoder using binary subgroup processing
- Patent number 9,748,974
- Issue date Aug 29, 2017
- Western Digital Technologies, Inc.
- Kasra Vakilinia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-binary LDPC decoder using binary subgroup processing
- Patent number 9,337,864
- Issue date May 10, 2016
- Western Digital Technologies, Inc.
- Kasra Vakilinia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced complexity non-binary LDPC decoding algorithm
- Patent number 9,319,069
- Issue date Apr 19, 2016
- HGST Technologies Santa Ana, Inc.
- Majid Nemati Anaraki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for soft decoding through single read
- Patent number 9,270,296
- Issue date Feb 23, 2016
- Western Digital Technologies, Inc.
- Majid Nemati Anaraki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-binary low-density parity check (LDPC) decoding using trellis m...
- Patent number 9,250,994
- Issue date Feb 2, 2016
- Western Digital Technologies, Inc.
- Kasra Vakilinia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for optimized soft decoding in a data storage device
- Patent number 9,007,854
- Issue date Apr 14, 2015
- Western Digital Technologies, Inc.
- Majid Nemati Anaraki
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced complexity non-binary LDPC decoding algorithm
- Patent number 8,954,820
- Issue date Feb 10, 2015
- Stec, Inc.
- Majid Nemati Anaraki
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TAPERED VARIABLE NODE MEMORY
- Publication number 20180191375
- Publication date Jul 5, 2018
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Jake BEAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL VARIABLE CODE RATE ERROR CORRECTION CODING
- Publication number 20180034476
- Publication date Feb 1, 2018
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Scott Thomas KAYSER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-BINARY LDPC DECODER USING BINARY SUBGROUP PROCESSING
- Publication number 20160329910
- Publication date Nov 10, 2016
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Kasra VAKILINIA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
- Publication number 20160233894
- Publication date Aug 11, 2016
- HGST Technologies Santa Ana, Inc.
- Majid NEMATI ANARAKI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
- Publication number 20150364202
- Publication date Dec 17, 2015
- HGST Technologies Santa Ana, Inc.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
- Publication number 20150143194
- Publication date May 21, 2015
- HGST NETHERLANDS B.V.
- Majid NEMATI ANARAKI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
- Publication number 20130212451
- Publication date Aug 15, 2013
- STEC, Inc.
- Majid NEMATI ANARAKI
- H03 - BASIC ELECTRONIC CIRCUITRY

Majid Nemati Anaraki

Person

Patents Grantslast 30 patents

Hierarchical variable code rate error correction coding

Tapered variable node memory

Non-binary LDPC decoder using binary subgroup processing

Non-binary LDPC decoder using binary subgroup processing

Reduced complexity non-binary LDPC decoding algorithm

Method and system for soft decoding through single read

Non-binary low-density parity check (LDPC) decoding using trellis m...

Method and system for optimized soft decoding in a data storage device

Reduced complexity non-binary LDPC decoding algorithm

Patents Applicationslast 30 patents

TAPERED VARIABLE NODE MEMORY

HIERARCHICAL VARIABLE CODE RATE ERROR CORRECTION CODING

NON-BINARY LDPC DECODER USING BINARY SUBGROUP PROCESSING

REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM

INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES

REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM

REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM