Manoj B. Roge

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,990,786
- Issue date Aug 2, 2011
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,983,094
- Issue date Jul 19, 2011
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
I/O block for high performance memory interfaces
- Patent number 7,928,770
- Issue date Apr 19, 2011
- Altera Corporation
- Andrew Bellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for fast cross row data access
- Patent number 7,660,167
- Issue date Feb 9, 2010
- Cypress Semiconductor Corporation
- Manoj Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,593,273
- Issue date Sep 22, 2009
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,590,008
- Issue date Sep 15, 2009
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device providing asynchronous and synchronous data transfer
- Patent number 6,791,898
- Issue date Sep 14, 2004
- Cypress Semiconductor Corporation
- Rajesh Manapat
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit encoded ternary content addressable memory cell
- Patent number 6,721,202
- Issue date Apr 13, 2004
- Cypress Semiconductor Corp.
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory cell
- Patent number 6,480,406
- Issue date Nov 12, 2002
- Cypress Semiconductor Corp.
- Bo Jin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable transmission line impedance matching circuit
- Patent number 6,384,621
- Issue date May 7, 2002
- Cypress Semiconductor Corp.
- Gary Gibbs
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20090296503
- Publication date Dec 3, 2009
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20080291758
- Publication date Nov 27, 2008
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY

Manoj B. Roge

Person

Patents Grantslast 30 patents

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

I/O block for high performance memory interfaces

Memory device and method for fast cross row data access

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

Memory device providing asynchronous and synchronous data transfer

Bit encoded ternary content addressable memory cell

Content addressable memory cell

Programmable transmission line impedance matching circuit

Patents Applicationslast 30 patents

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA