Manuj AYODHYAWASI

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive bit line overdrive control for an in-memory compute operat...
- Patent number 11,984,151
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable clock adaptation in neural network processors
- Patent number 11,900,240
- Issue date Feb 13, 2024
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tagged memory operated at lower vmin in error tolerant system
- Patent number 11,836,346
- Issue date Dec 5, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tagged memory operated at lower vmin in error tolerant system
- Patent number 11,360,667
- Issue date Jun 14, 2022
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...
- Publication number 20240177769
- Publication date May 30, 2024
- STMicroelectronics International N.V.
- Promod KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...
- Publication number 20240143239
- Publication date May 2, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240069096
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071429
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071439
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20240045589
- Publication date Feb 8, 2024
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...
- Publication number 20230410892
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230410862
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...
- Publication number 20230386566
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230386565
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230386564
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20230102492
- Publication date Mar 30, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...
- Publication number 20230012567
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230009329
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20230008833
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230012303
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230008275
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20220269410
- Publication date Aug 25, 2022
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE CLOCK ADAPTATION IN NEURAL NETWORK PROCESSORS
- Publication number 20210081773
- Publication date Mar 18, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20210072894
- Publication date Mar 11, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING

Manuj AYODHYAWASI

Person

Patents Grantslast 30 patents

Serial word line actuation with linked source voltage supply modula...

Adaptive bit line overdrive control for an in-memory compute operat...

Variable clock adaptation in neural network processors

Tagged memory operated at lower vmin in error tolerant system

Tagged memory operated at lower vmin in error tolerant system

Patents Applicationslast 30 patents

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...

ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

VARIABLE CLOCK ADAPTATION IN NEURAL NETWORK PROCESSORS

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM