Marc Dittes

Person

Regensburg, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,955,462
- Issue date Apr 9, 2024
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,239,199
- Issue date Feb 1, 2022
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,816,742
- Issue date Oct 27, 2020
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Semiconductor package having a variable redistribution layer thickness
- Patent number 10,553,538
- Issue date Feb 4, 2020
- Intel Corporation
- Klaus Jürgen Reingruber
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Electrical device and a method for forming an electrical device
- Patent number 10,522,485
- Issue date Dec 31, 2019
- Intel IP Corporation
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical wire connections for integrated circuit package
- Patent number 10,490,527
- Issue date Nov 26, 2019
- Intel IP Corporation
- Christian Geissler
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic package with illuminated backside exterior
- Patent number 10,411,000
- Issue date Sep 10, 2019
- Intel IP Corporation
- Marc Stephan Dittes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System-in-package devices and methods for forming system-in-package...
- Patent number 10,403,609
- Issue date Sep 3, 2019
- Intel IP Corporation
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,209,466
- Issue date Feb 19, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Substrate and method for fabrication thereof
- Patent number 10,181,439
- Issue date Jan 15, 2019
- Infineon Technologies AG
- Carlo Marbella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having a variable redistribution layer thickness
- Patent number 10,115,668
- Issue date Oct 30, 2018
- Intel IP Corporation
- Klaus Jürgen Reingruber
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20240213225
- Publication date Jun 27, 2024
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20220108976
- Publication date Apr 7, 2022
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL FIBER CONNECTION ON PACKAGE EDGE
- Publication number 20190121041
- Publication date Apr 25, 2019
- Intel IP Corporation
- Sven Albers
- G02 - OPTICS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER
- Publication number 20190072732
- Publication date Mar 7, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS
- Publication number 20190043800
- Publication date Feb 7, 2019
- Intel IP Corporation
- Klaus Jürgen REINGRUBER
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE
- Publication number 20180374819
- Publication date Dec 27, 2018
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System-in-Package Devices and Methods for Forming System-in-Package...
- Publication number 20180331080
- Publication date Nov 15, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical device and a method for forming an electrical device
- Publication number 20180331053
- Publication date Nov 15, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20180331070
- Publication date Nov 15, 2018
- Intel IP Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE AND METHOD FOR FABRICATION THEREOF
- Publication number 20180315692
- Publication date Nov 1, 2018
- INFINEON TECHNOLOGIES AG
- Carlo Marbella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER
- Publication number 20170285280
- Publication date Oct 5, 2017
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Application
Microelectronic Package with Illuminated Backside Exterior
- Publication number 20170284636
- Publication date Oct 5, 2017
- Intel IP Corporation
- Marc Stephan Dittes
- F21 - LIGHTING
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS
- Publication number 20170170111
- Publication date Jun 15, 2017
- Intel IP Corporation
- Klaus Jürgen REINGRUBER
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR

Marc Dittes

Person

Patents Grantslast 30 patents

Package stacking using chip to wafer bonding

Package stacking using chip to wafer bonding

Integrated circuit packages including an optical redistribution layer

Semiconductor package having a variable redistribution layer thickness

Electrical device and a method for forming an electrical device

Vertical wire connections for integrated circuit package

Microelectronic package with illuminated backside exterior

System-in-package devices and methods for forming system-in-package...

Integrated circuit packages including an optical redistribution layer

Substrate and method for fabrication thereof

Semiconductor package having a variable redistribution layer thickness

Patents Applicationslast 30 patents

PACKAGE STACKING USING CHIP TO WAFER BONDING

PACKAGE STACKING USING CHIP TO WAFER BONDING

OPTICAL FIBER CONNECTION ON PACKAGE EDGE

INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER

SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS

VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE

System-in-Package Devices and Methods for Forming System-in-Package...

Electrical device and a method for forming an electrical device

PACKAGE STACKING USING CHIP TO WAFER BONDING

SUBSTRATE AND METHOD FOR FABRICATION THEREOF

INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER

Microelectronic Package with Illuminated Backside Exterior

SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS