Marco Casarsa

Person

Vaprio d'Adda (MI), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Random access memory and corresponding method for managing a random...
- Patent number 12,073,897
- Issue date Aug 27, 2024
- STMicroelectronics S.r.l.
- Marco Casarsa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 11,747,398
- Issue date Sep 5, 2023
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
System for performing the test of digital circuits
- Patent number 8,996,939
- Issue date Mar 31, 2015
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Electrical interconnection integrated device with fault detecting m...
- Patent number 8,618,812
- Issue date Dec 31, 2013
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Shared diagnosis method for an integrated electronic system includi...
- Patent number 8,099,640
- Issue date Jan 17, 2012
- STMicroelectronics S.r.l.
- Marco Casarsa
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous set-reset circuit device
- Patent number 7,941,715
- Issue date May 10, 2011
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain architecture for increased diagnostic capability in digi...
- Patent number 7,900,103
- Issue date Mar 1, 2011
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression architecture for a design for testability compiler...
- Patent number 7,702,983
- Issue date Apr 20, 2010
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Grant
Integrated device with an improved BIST circuit for executing a str...
- Patent number 7,246,288
- Issue date Jul 17, 2007
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM...
- Publication number 20240404613
- Publication date Dec 5, 2024
- STMicroelectronics S.r.l.
- Marco Casarsa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD
- Publication number 20230358806
- Publication date Nov 9, 2023
- STMicroelectronics S.r.l.
- Marco CASARSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM...
- Publication number 20230343405
- Publication date Oct 26, 2023
- STMicroelectronics S.r.l.
- Marco Casarsa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD
- Publication number 20220263499
- Publication date Aug 18, 2022
- STMicroelectronics S.r.l.
- Marco CASARSA
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR PERFORMING THE TEST OF DIGITAL CIRCUITS
- Publication number 20110258499
- Publication date Oct 20, 2011
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Application
ELECTRICAL INTERCONNECTION INTEGRATED DEVICE WITH FAULT DETECTING M...
- Publication number 20110187384
- Publication date Aug 4, 2011
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Application
SHARED DIAGNOSIS METHOD FOR AN INTEGRATED ELECTRONIC SYSTEM INCLUDI...
- Publication number 20100058128
- Publication date Mar 4, 2010
- STMicroelectronics S.r.l.
- Marco CASARSA
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN ARCHITECTURE FOR INCREASED DIAGNOSTIC CAPABILITY IN DIGI...
- Publication number 20080155365
- Publication date Jun 26, 2008
- STMicroelectronics S.r.I.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Application
ASYNCHRONOUS SET-RESET CIRCUIT DEVICE
- Publication number 20070300116
- Publication date Dec 27, 2007
- STMicroelectronics S.r.I.
- Marco CASARSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN COMPRESSION ARCHITECTURE FOR A DESIGN FOR TESTABILITY COMPILER...
- Publication number 20070283200
- Publication date Dec 6, 2007
- STMicroelectronics S.r.l.
- Marco Casarsa
- G01 - MEASURING TESTING
Information Patent Application
Integrated device with an improved BIST circuit for executing a str...
- Publication number 20050034041
- Publication date Feb 10, 2005
- STMicroelectronics S.r. I.
- Marco Casarsa
- G01 - MEASURING TESTING

Marco Casarsa

Person

Patents Grantslast 30 patents

Random access memory and corresponding method for managing a random...

Scan chain circuit and corresponding method

System for performing the test of digital circuits

Electrical interconnection integrated device with fault detecting m...

Shared diagnosis method for an integrated electronic system includi...

Asynchronous set-reset circuit device

Scan chain architecture for increased diagnostic capability in digi...

Scan compression architecture for a design for testability compiler...

Integrated device with an improved BIST circuit for executing a str...

Patents Applicationslast 30 patents

RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM...

SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD

RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM...

SCAN CHAIN CIRCUIT AND CORRESPONDING METHOD

SYSTEM FOR PERFORMING THE TEST OF DIGITAL CIRCUITS

ELECTRICAL INTERCONNECTION INTEGRATED DEVICE WITH FAULT DETECTING M...

SHARED DIAGNOSIS METHOD FOR AN INTEGRATED ELECTRONIC SYSTEM INCLUDI...

SCAN CHAIN ARCHITECTURE FOR INCREASED DIAGNOSTIC CAPABILITY IN DIGI...

ASYNCHRONOUS SET-RESET CIRCUIT DEVICE

SCAN COMPRESSION ARCHITECTURE FOR A DESIGN FOR TESTABILITY COMPILER...

Integrated device with an improved BIST circuit for executing a str...