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Margaret Martonosi
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Princeton, NJ, US
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last 30 patents
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Patent Grant
Method and apparatus for SAT solver architecture with very low synt...
Patent number
6,415,430
Issue date
Jul 2, 2002
NEC USA, Inc.
Pranav Ashar
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Method and apparatus for edge-endpoint-based VLSI design rule checking
Patent number
6,324,673
Issue date
Nov 27, 2001
Princeton University
Zhen Luo
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Configurable hardware system implementing Boolean Satisfiability an...
Patent number
6,247,164
Issue date
Jun 12, 2001
NEC USA, Inc.
Pranav Ashar
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Implementation of boolean satisfiability with non-chronological bac...
Patent number
6,038,392
Issue date
Mar 14, 2000
NEC USA, Inc.
Pranav Ashar
G06 - COMPUTING CALCULATING COUNTING