Maria Luisa Gallese

Person

Avezzano, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Power down/power-loss memory controller
- Patent number 10,528,292
- Issue date Jan 7, 2020
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for providing redundancy in memory
- Patent number 10,446,258
- Issue date Oct 15, 2019
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Single node power management for multiple memory devices
- Patent number 10,170,167
- Issue date Jan 1, 2019
- Micron Technology, Inc.
- Mauro Castelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices for reading memory cells of different memory planes
- Patent number 10,037,809
- Issue date Jul 31, 2018
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for providing redundancy in a memory array comprising mappi...
- Patent number 9,779,839
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices for reading memory cells of different memory planes
- Patent number 9,779,826
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrently reading first and second pages of memory cells having...
- Patent number 9,754,674
- Issue date Sep 5, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controllers
- Patent number 9,513,912
- Issue date Dec 6, 2016
- Micron Technology, Inc.
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrently reading first and second pages of memory cells having...
- Patent number 9,502,125
- Issue date Nov 22, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory area protection system and methods
- Patent number 9,406,388
- Issue date Aug 2, 2016
- Micron Technology, Inc.
- Luca De Santis
- G11 - INFORMATION STORAGE
Information Patent Grant
Single node power management for multiple memory devices
- Patent number 9,349,423
- Issue date May 24, 2016
- Micron Technology, Inc.
- Mauro Castelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for providing redundancy and apparatuses
- Patent number 9,202,569
- Issue date Dec 1, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Data interleaving module
- Patent number 9,189,440
- Issue date Nov 17, 2015
- Micron Technology, Inc.
- Luigi Pilolli
- G11 - INFORMATION STORAGE
Information Patent Grant
Data interleaving module
- Patent number 8,804,452
- Issue date Aug 12, 2014
- Micron Technology, Inc.
- Luigi Pilolli
- G11 - INFORMATION STORAGE
Information Patent Grant
Background block erase check for flash memories
- Patent number 7,117,402
- Issue date Oct 3, 2006
- Micron Technology, Inc.
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
POWER-DOWN/POWER-LOSS MEMORY CONTROLLER
- Publication number 20190042156
- Publication date Feb 7, 2019
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR READING MEMORY CELLS OF DIFFERENT MEMORY PLANES
- Publication number 20180075913
- Publication date Mar 15, 2018
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY
- Publication number 20180047460
- Publication date Feb 15, 2018
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING...
- Publication number 20170025181
- Publication date Jan 26, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE NODE POWER MANAGEMENT FOR MULTIPLE MEMORY DEVICES
- Publication number 20160267953
- Publication date Sep 15, 2016
- Micron Technology, Inc.
- Mauro Castelli
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING...
- Publication number 20160071605
- Publication date Mar 10, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY
- Publication number 20160071619
- Publication date Mar 10, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE NODE POWER MANAGEMENT FOR MULTIPLE MEMORY DEVICES
- Publication number 20160064052
- Publication date Mar 3, 2016
- Micron Technology, Inc.
- Mauro Castelli
- G11 - INFORMATION STORAGE
Information Patent Application
DATA INTERLEAVING MODULE
- Publication number 20150019787
- Publication date Jan 15, 2015
- Micron Technology, Inc.
- Luigi Pilolli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INTERLEAVING MODULE
- Publication number 20140040571
- Publication date Feb 6, 2014
- Micron Technology, Inc.
- Luigi Pilolli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLERS
- Publication number 20140032886
- Publication date Jan 30, 2014
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES
- Publication number 20130039138
- Publication date Feb 14, 2013
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Area Protection System and Methods
- Publication number 20100138623
- Publication date Jun 3, 2010
- Micron Technology, Inc.
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERNAL FAIL BIT OR BYTE COUNTER
- Publication number 20100031096
- Publication date Feb 4, 2010
- Ercole Rosario Di Iorio
- G11 - INFORMATION STORAGE
Information Patent Application
Background block erase check for flash memories
- Publication number 20030101390
- Publication date May 29, 2003
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE

Maria Luisa Gallese

Person

Patents Grantslast 30 patents

Power down/power-loss memory controller

Methods and apparatus for providing redundancy in memory

Single node power management for multiple memory devices

Memory devices for reading memory cells of different memory planes

Methods for providing redundancy in a memory array comprising mappi...

Memory devices for reading memory cells of different memory planes

Concurrently reading first and second pages of memory cells having...

Memory controllers

Concurrently reading first and second pages of memory cells having...

Memory area protection system and methods

Single node power management for multiple memory devices

Methods for providing redundancy and apparatuses

Data interleaving module

Data interleaving module

Background block erase check for flash memories

Patents Applicationslast 30 patents

POWER-DOWN/POWER-LOSS MEMORY CONTROLLER

MEMORY DEVICES FOR READING MEMORY CELLS OF DIFFERENT MEMORY PLANES

METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY

CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING...

SINGLE NODE POWER MANAGEMENT FOR MULTIPLE MEMORY DEVICES

CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING...

METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY

SINGLE NODE POWER MANAGEMENT FOR MULTIPLE MEMORY DEVICES

DATA INTERLEAVING MODULE

DATA INTERLEAVING MODULE

MEMORY CONTROLLERS

METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES

Memory Area Protection System and Methods

INTERNAL FAIL BIT OR BYTE COUNTER

Background block erase check for flash memories