Mario Fulam Au

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-queue address generator for start and end addresses in a mult...
- Patent number 8,230,174
- Issue date Jul 24, 2012
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial buffer supporting virtual queue to physical memory mapping
- Patent number 7,945,716
- Issue date May 17, 2011
- Integrated Device Technology, Inc.
- Chi-Lie Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple counters to relieve flag restriction in a multi-queue firs...
- Patent number 7,870,310
- Issue date Jan 11, 2011
- Integrated Device Technology, Inc.
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-function queue to support data offload, protocol translation...
- Patent number 7,805,551
- Issue date Sep 28, 2010
- Integrated Device Technology, Inc.
- Chi-Lie Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Partial packet write and write data filtering in a multi-queue firs...
- Patent number 7,805,552
- Issue date Sep 28, 2010
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output drive circuit that accommodates variable supply voltages
- Patent number 7,586,343
- Issue date Sep 8, 2009
- Integrated Device Technology, Inc.
- David Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed, low-power level shifter for mixed signal-level environm...
- Patent number 7,554,379
- Issue date Jun 30, 2009
- Integrated Device Technology, Inc.
- David J. Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mark/re-read and mark/re-write operations in a multi-queue first-in...
- Patent number 7,523,232
- Issue date Apr 21, 2009
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-queue FIFO memory devices that support a backed-off standard...
- Patent number 7,392,354
- Issue date Jun 24, 2008
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Status bus accessing only available quadrants during loop mode oper...
- Patent number 7,269,700
- Issue date Sep 11, 2007
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of active flag and status bus flags in a multi-queu...
- Patent number 7,257,687
- Issue date Aug 14, 2007
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential flow-control and FIFO memory devices having error detect...
- Patent number 7,246,300
- Issue date Jul 17, 2007
- Integrated Device Technology Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output drive circuit that accommodates variable supply voltages
- Patent number 7,224,195
- Issue date May 29, 2007
- Integrated Device Technology, Inc.
- David Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential flow-control and FIFO memory devices that are depth expa...
- Patent number 7,209,983
- Issue date Apr 24, 2007
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices having write and read control circuits that sup...
- Patent number 7,158,440
- Issue date Jan 2, 2007
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed multiple blanking for noise suppression during flag gene...
- Patent number 7,154,327
- Issue date Dec 26, 2006
- Integrated Device Technology, Inc.
- Jason Z. Mo
- G11 - INFORMATION STORAGE
Information Patent Grant
Interleaving memory blocks to relieve timing bottleneck in a multi-...
- Patent number 7,099,231
- Issue date Aug 29, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory devices having clock signal arbitration c...
- Patent number 7,093,047
- Issue date Aug 15, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated DDR/SDR flow control managers that support multiple queu...
- Patent number 7,082,071
- Issue date Jul 25, 2006
- Integrated Device Technology, Inc.
- Roland T. Knaack
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices having multi-port cache memory arrays therein t...
- Patent number 7,076,610
- Issue date Jul 11, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port memory cells for use in FIFO applications that support d...
- Patent number 7,042,792
- Issue date May 9, 2006
- Integrated Device Technology, Inc.
- Shih-Ked Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
FIFO memory devices having multi-port cache and extended capacity m...
- Patent number 6,874,064
- Issue date Mar 29, 2005
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fifo memory devices that support all four combinations of DDR or SD...
- Patent number 6,795,360
- Issue date Sep 21, 2004
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices that support all combinations of DDR and SDR re...
- Patent number 6,778,454
- Issue date Aug 17, 2004
- Integrated Device Technology, Inc.
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices and methods of operating FIFO memory devices ha...
- Patent number 6,754,777
- Issue date Jun 22, 2004
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port cache memory devices and FIFO memory devices having mult...
- Patent number 6,546,461
- Issue date Apr 8, 2003
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for byte alignment operations for a memory dev...
- Patent number 6,539,465
- Issue date Mar 25, 2003
- Integrated Device Technology, Inc.
- Raymond K. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for byte alignment operations for a memory de...
- Patent number 6,243,799
- Issue date Jun 5, 2001
- Integrated Device Technology, Inc.
- Raymond K. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for providing logical cell available informat...
- Patent number 6,230,249
- Issue date May 8, 2001
- Integrated Device Technology, Inc.
- Raymond K. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for a memory that supports a variable number...
- Patent number 6,122,717
- Issue date Sep 19, 2000
- Integrated Device Technology, Inc.
- Raymond K. Chan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Multi-Function Queue To Support Data Offload, Protocol Translation...
- Publication number 20090086748
- Publication date Apr 2, 2009
- Integrated Device Technology, Inc.
- Chi-Lie Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Serial Buffer Supporting Virtual Queue To Physical Memory Mapping
- Publication number 20090089532
- Publication date Apr 2, 2009
- Integrated Device Technology, Inc.
- Chi-Lie Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-performance level shifter
- Publication number 20080204109
- Publication date Aug 28, 2008
- David J. Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Output drive circuit that accommodates variable supply voltages
- Publication number 20070285135
- Publication date Dec 13, 2007
- Integrated Device Technology, Inc.
- David Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-queue FIFO memory systems that utilize read chip select and d...
- Publication number 20060155940
- Publication date Jul 13, 2006
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synchronization of active flag and status bus flags in a multi-queu...
- Publication number 20060020741
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Status bus accessing only available quadrants during loop mode oper...
- Publication number 20060020742
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-queue address generator for start and end addresses in a mult...
- Publication number 20060020743
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleaving memory blocks to relieve timing bottleneck in a multi-...
- Publication number 20060018170
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Application
Mark/re-read and mark/re-write operations in a multi-queue first-in...
- Publication number 20060018176
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partial packet read/write and data filtering in a multi-queue first...
- Publication number 20060020761
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple counters to relieve flag restriction in a multi-queue firs...
- Publication number 20060018177
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-timed multiple blanking for noise suppression during flag gene...
- Publication number 20060017497
- Publication date Jan 26, 2006
- Integrated Device Technology, Inc.
- Jason Z. Mo
- G11 - INFORMATION STORAGE
Information Patent Application
Output drive circuit that accommodates variable supply voltages
- Publication number 20050184768
- Publication date Aug 25, 2005
- David Pilling
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-port memory cells for use in FIFO applications that support d...
- Publication number 20050152204
- Publication date Jul 14, 2005
- Shih-Ked Lee
- G11 - INFORMATION STORAGE
Information Patent Application
FIFO memory devices having write and read control circuits that sup...
- Publication number 20050041450
- Publication date Feb 24, 2005
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated DDR/SDR flow control managers that support multiple queu...
- Publication number 20050018514
- Publication date Jan 27, 2005
- Roland T. Knaack
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit memory devices having clock signal arbitration c...
- Publication number 20050005069
- Publication date Jan 6, 2005
- Mario Au
- G11 - INFORMATION STORAGE
Information Patent Application
Sequential flow-control and FIFO memory devices that are depth expa...
- Publication number 20050005082
- Publication date Jan 6, 2005
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fifo memory devices having multi-port cache and extended capacity m...
- Publication number 20040193805
- Publication date Sep 30, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040047209
- Publication date Mar 11, 2004
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040019743
- Publication date Jan 29, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices that support all combinations of DDR and SDR re...
- Publication number 20030206475
- Publication date Nov 6, 2003
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices having single data rate (SDR) and dual data rat...
- Publication number 20030112685
- Publication date Jun 19, 2003
- Jiann-Jeng Duh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for byte alignment operations for a memory de...
- Publication number 20010032302
- Publication date Oct 18, 2001
- Raymond K. Chan
- G06 - COMPUTING CALCULATING COUNTING

Mario Fulam Au

Person

Patents Grantslast 30 patents

Multi-queue address generator for start and end addresses in a mult...

Serial buffer supporting virtual queue to physical memory mapping

Multiple counters to relieve flag restriction in a multi-queue firs...

Multi-function queue to support data offload, protocol translation...

Partial packet write and write data filtering in a multi-queue firs...

Output drive circuit that accommodates variable supply voltages

High-speed, low-power level shifter for mixed signal-level environm...

Mark/re-read and mark/re-write operations in a multi-queue first-in...

Multi-queue FIFO memory devices that support a backed-off standard...

Status bus accessing only available quadrants during loop mode oper...

Synchronization of active flag and status bus flags in a multi-queu...

Sequential flow-control and FIFO memory devices having error detect...

Output drive circuit that accommodates variable supply voltages

Sequential flow-control and FIFO memory devices that are depth expa...

FIFO memory devices having write and read control circuits that sup...

Self-timed multiple blanking for noise suppression during flag gene...

Interleaving memory blocks to relieve timing bottleneck in a multi-...

Integrated circuit memory devices having clock signal arbitration c...

Integrated DDR/SDR flow control managers that support multiple queu...

FIFO memory devices having multi-port cache memory arrays therein t...

Multi-port memory cells for use in FIFO applications that support d...

FIFO memory devices having multi-port cache and extended capacity m...

Fifo memory devices that support all four combinations of DDR or SD...

FIFO memory devices that support all combinations of DDR and SDR re...

FIFO memory devices and methods of operating FIFO memory devices ha...

Multi-port cache memory devices and FIFO memory devices having mult...

Method and apparatus for byte alignment operations for a memory dev...

Methods and apparatus for byte alignment operations for a memory de...

Methods and apparatus for providing logical cell available informat...

Methods and apparatus for a memory that supports a variable number...

Patents Applicationslast 30 patents

Multi-Function Queue To Support Data Offload, Protocol Translation...

Serial Buffer Supporting Virtual Queue To Physical Memory Mapping

High-performance level shifter

Output drive circuit that accommodates variable supply voltages

Multi-queue FIFO memory systems that utilize read chip select and d...

Synchronization of active flag and status bus flags in a multi-queu...

Status bus accessing only available quadrants during loop mode oper...

Multi-queue address generator for start and end addresses in a mult...

Interleaving memory blocks to relieve timing bottleneck in a multi-...

Mark/re-read and mark/re-write operations in a multi-queue first-in...

Partial packet read/write and data filtering in a multi-queue first...

Multiple counters to relieve flag restriction in a multi-queue firs...

Self-timed multiple blanking for noise suppression during flag gene...

Output drive circuit that accommodates variable supply voltages

Multi-port memory cells for use in FIFO applications that support d...

FIFO memory devices having write and read control circuits that sup...

Integrated DDR/SDR flow control managers that support multiple queu...

Integrated circuit memory devices having clock signal arbitration c...

Sequential flow-control and FIFO memory devices that are depth expa...

Fifo memory devices having multi-port cache and extended capacity m...

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices that support all combinations of DDR and SDR re...

FIFO memory devices having single data rate (SDR) and dual data rat...

Methods and apparatus for byte alignment operations for a memory de...