Marios C. Papaefthymiou

Person

Ann Arbor, MI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resonant clock distribution network architecture for tracking param...
- Patent number 9,041,451
- Issue date May 26, 2015
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock distribution network architecture with programmable...
- Patent number 8,659,338
- Issue date Feb 25, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for controlling clock characteristics
- Patent number 8,593,183
- Issue date Nov 26, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for operating resonant clock network in conventional mode
- Patent number 8,502,569
- Issue date Aug 6, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock and interconnect architecture for digital devices wi...
- Patent number 8,461,873
- Issue date Jun 11, 2013
- Cyclos Semiconductor, Inc.
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for frequency-scaled operation in resonant clock distr...
- Patent number 8,400,192
- Issue date Mar 19, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for adjusting natural frequency in resonant clock dist...
- Patent number 8,368,450
- Issue date Feb 5, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for single-stepping in resonant clock distribution net...
- Patent number 8,362,811
- Issue date Jan 29, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock distribution network architecture for tracking param...
- Patent number 8,358,163
- Issue date Jan 22, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for selecting natural frequency in resonant clock distributi...
- Patent number 8,339,209
- Issue date Dec 25, 2012
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock distribution network architecture with clock skew management
- Patent number 8,289,063
- Issue date Oct 16, 2012
- The Regents of the University of Michigan
- Juang-Ying Chueh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resonant clock and interconnect architecture for digital devices wi...
- Patent number 7,973,565
- Issue date Jul 5, 2011
- Cyclos Semiconductor, Inc.
- Alexander Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network architecture with clock skew management
- Patent number 7,956,664
- Issue date Jun 7, 2011
- The Regents of the University of Michigan
- Juang-Ying Chueh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock distribution network architecture for resonant-clocked systems
- Patent number 7,719,316
- Issue date May 18, 2010
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network architecture with resonant clock gating
- Patent number 7,719,317
- Issue date May 18, 2010
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ramped clock digital storage control
- Patent number 7,622,977
- Issue date Nov 24, 2009
- The Regents of the University of Michigan
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Energy recovery boost logic
- Patent number 7,355,454
- Issue date Apr 8, 2008
- The Regents of the University of Michigan
- Marios C. Papaefthymiou
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Low-power driver with energy recovery
- Patent number 6,879,190
- Issue date Apr 12, 2005
- The Regents of the University of Michigan
- Joohee Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power CMOS flip-flop
- Patent number 6,777,992
- Issue date Aug 17, 2004
- The Regents of the University of Michigan
- Conrad H. Ziesler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating a clock signal having a driven...
- Patent number 6,742,132
- Issue date May 25, 2004
- The Regents of the University of Michigan
- Conrad H. Ziesler
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPUTATIONAL SPRINTING USING MULTIPLE CORES
- Publication number 20140317389
- Publication date Oct 23, 2014
- The Trustees of the University of Pennsylvania
- Thomas F. Wenisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resonant Clock Distribution Network Architecture for Tracking Param...
- Publication number 20140015585
- Publication date Jan 16, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for Single-Stepping in Resonant Clock Distribution Net...
- Publication number 20140002175
- Publication date Jan 2, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for Adjusting Natural Frequency in Resonant Clock Dist...
- Publication number 20130328608
- Publication date Dec 12, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Selecting Natural Frequency in Resonant Clock Distributi...
- Publication number 20130194018
- Publication date Aug 1, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network Architecture with Clock Skew Management
- Publication number 20110215854
- Publication date Sep 8, 2011
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resonant Clock And Interconnect Architecture For Digital Devices Wi...
- Publication number 20110210761
- Publication date Sep 1, 2011
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE...
- Publication number 20110140753
- Publication date Jun 16, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR ADJUSTING NATURAL FREQUENCY IN RESONANT CLOCK DIST...
- Publication number 20110090018
- Publication date Apr 21, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR FREQUENCY-SCALED OPERATION IN RESONANT CLOCK DISTR...
- Publication number 20110090019
- Publication date Apr 21, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS
- Publication number 20110084736
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTI...
- Publication number 20110084772
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NET...
- Publication number 20110084773
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE
- Publication number 20110084774
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAM...
- Publication number 20110084775
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WI...
- Publication number 20090027085
- Publication date Jan 29, 2009
- Cyclos Semiconductor, Inc.
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network Architecture for Resonant-Clocked Systems
- Publication number 20080303552
- Publication date Dec 11, 2008
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network Architecture with Resonant Clock Gating
- Publication number 20080303576
- Publication date Dec 11, 2008
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network Architecture with Clock Skew Management
- Publication number 20080150605
- Publication date Jun 26, 2008
- The Regents of the University of Michigan
- Juang-Ying Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ramped Clock Digital Storage Control
- Publication number 20070096957
- Publication date May 3, 2007
- The Regents of the University of Michigan
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Energy recovery boost logic
- Publication number 20060082387
- Publication date Apr 20, 2006
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low-power driver with energy recovery
- Publication number 20030201803
- Publication date Oct 30, 2003
- Joohee Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Low-power CMOS flip-flop
- Publication number 20030189451
- Publication date Oct 9, 2003
- The Regents of the University of Michigan
- Conrad H. Ziesler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock signal generating circuit
- Publication number 20030191977
- Publication date Oct 9, 2003
- The Regents of the University of Michigan
- Conrad Havluj Ziesler
- G06 - COMPUTING CALCULATING COUNTING

Marios C. Papaefthymiou

Person

Patents Grantslast 30 patents

Resonant clock distribution network architecture for tracking param...

Resonant clock distribution network architecture with programmable...

Architecture for controlling clock characteristics

Architecture for operating resonant clock network in conventional mode

Resonant clock and interconnect architecture for digital devices wi...

Architecture for frequency-scaled operation in resonant clock distr...

Architecture for adjusting natural frequency in resonant clock dist...

Architecture for single-stepping in resonant clock distribution net...

Resonant clock distribution network architecture for tracking param...

Method for selecting natural frequency in resonant clock distributi...

Clock distribution network architecture with clock skew management

Resonant clock and interconnect architecture for digital devices wi...

Clock distribution network architecture with clock skew management

Clock distribution network architecture for resonant-clocked systems

Clock distribution network architecture with resonant clock gating

Ramped clock digital storage control

Energy recovery boost logic

Low-power driver with energy recovery

Low-power CMOS flip-flop

Method and apparatus for generating a clock signal having a driven...

Patents Applicationslast 30 patents

COMPUTATIONAL SPRINTING USING MULTIPLE CORES

Resonant Clock Distribution Network Architecture for Tracking Param...

Architecture for Single-Stepping in Resonant Clock Distribution Net...

Architecture for Adjusting Natural Frequency in Resonant Clock Dist...

Method for Selecting Natural Frequency in Resonant Clock Distributi...

Clock Distribution Network Architecture with Clock Skew Management

Resonant Clock And Interconnect Architecture For Digital Devices Wi...

RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE...

ARCHITECTURE FOR ADJUSTING NATURAL FREQUENCY IN RESONANT CLOCK DIST...

ARCHITECTURE FOR FREQUENCY-SCALED OPERATION IN RESONANT CLOCK DISTR...

ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS

METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTI...

ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NET...

ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE

RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAM...

RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WI...

Clock Distribution Network Architecture for Resonant-Clocked Systems

Clock Distribution Network Architecture with Resonant Clock Gating

Clock Distribution Network Architecture with Clock Skew Management

Ramped Clock Digital Storage Control

Energy recovery boost logic

Low-power driver with energy recovery

Low-power CMOS flip-flop

Clock signal generating circuit