Mark A. Hawes

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory array reset read operation
- Patent number 12,119,051
- Issue date Oct 15, 2024
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Grant
Read retry scratch space
- Patent number 12,111,725
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Rahul Mitchell Jairaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for establishing a negative body potential in a memory cell
- Patent number 11,710,525
- Issue date Jul 25, 2023
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Read retry scratch space
- Patent number 11,586,498
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Rahul Mitchell Jairaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array reset read operation
- Patent number 11,423,976
- Issue date Aug 23, 2022
- Micron Technology, Inc.
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including establishing a negative body potent...
- Patent number 10,916,313
- Issue date Feb 9, 2021
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array reset read operation
- Patent number 10,685,702
- Issue date Jun 16, 2020
- Micron Technology, Inc.
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including establishing a negative body potent...
- Patent number 10,453,538
- Issue date Oct 22, 2019
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods including establishing a negative body potential in a memor...
- Patent number 10,049,750
- Issue date Aug 14, 2018
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining soft data for combinations of memory cells
- Patent number 9,543,000
- Issue date Jan 10, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining soft data for combinations of memory cells
- Patent number 9,230,661
- Issue date Jan 5, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Loading trim address and trim data pairs
- Patent number 9,007,867
- Issue date Apr 14, 2015
- Micron Technology, Inc.
- Mark Hawes
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining soft data for combinations of memory cells
- Patent number 8,737,139
- Issue date May 27, 2014
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory block testing
- Patent number 8,094,508
- Issue date Jan 10, 2012
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory block testing
- Patent number 7,567,472
- Issue date Jul 28, 2009
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Die based trimming
- Patent number 7,512,507
- Issue date Mar 31, 2009
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Output data compression scheme for use in testing IC memories
- Patent number 6,016,561
- Issue date Jan 18, 2000
- Micron Technology, Inc.
- Fariborz F. Roohparvar
- G11 - INFORMATION STORAGE
Information Patent Grant
Output data compression scheme for use in testing IC memories
- Patent number 5,787,097
- Issue date Jul 28, 1998
- Micron Technology, Inc.
- Fariborz F. Roohparvar
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device macrocell having exclusive lines for feed...
- Patent number 5,414,376
- Issue date May 9, 1995
- Micron Semiconductor, Inc.
- Mark A. Hawes
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device macrocell with an exclusive feedback and...
- Patent number 5,384,500
- Issue date Jan 24, 1995
- Micron Semiconductor, Inc.
- Mark A. Hawes
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device macrocell with an exclusive feedback line...
- Patent number 5,331,227
- Issue date Jul 19, 1994
- Micron Semiconductor, Inc.
- Mark A. Hawes
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device macrocell with an exclusive feedback and...
- Patent number 5,300,830
- Issue date Apr 5, 1994
- Micron Semiconductor, Inc.
- Mark A. Hawes
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
READ RETRY SCRATCH SPACE
- Publication number 20230205628
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Rahul Mitchell Jairaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY RESET READ OPERATION
- Publication number 20220383949
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR ESTABLISHING A NEGATIVE BODY POTENTIAL IN A MEMORY CELL
- Publication number 20210134373
- Publication date May 6, 2021
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Application
READ RETRY SCRATCH SPAC
- Publication number 20200371876
- Publication date Nov 26, 2020
- Micron Technology, Inc.
- Rahul Mitchell Jairaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY RESET READ OPERATION
- Publication number 20200365201
- Publication date Nov 19, 2020
- Micron Technology, Inc.
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...
- Publication number 20200143894
- Publication date May 7, 2020
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY RESET READ OPERATION
- Publication number 20190066771
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...
- Publication number 20180322930
- Publication date Nov 8, 2018
- Micron Technology, Inc.
- Koji Sakui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...
- Publication number 20180137922
- Publication date May 17, 2018
- Micron Technology, Inc.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS
- Publication number 20160104526
- Publication date Apr 14, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS
- Publication number 20140321207
- Publication date Oct 30, 2014
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
LOADING TRIM ADDRESS AND TRIM DATA PAIRS
- Publication number 20140241097
- Publication date Aug 28, 2014
- Mark Hawes
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS
- Publication number 20130272071
- Publication date Oct 17, 2013
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BLOCK TESTING
- Publication number 20090290441
- Publication date Nov 26, 2009
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE
Information Patent Application
Memory block testing
- Publication number 20070266276
- Publication date Nov 15, 2007
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE
Information Patent Application
DIE BASED TRIMMING
- Publication number 20070225928
- Publication date Sep 27, 2007
- Micron Technology, Inc.
- Scott N. Gatzemeier
- G11 - INFORMATION STORAGE

Mark A. Hawes

Person

Patents Grantslast 30 patents

Memory array reset read operation

Read retry scratch space

Apparatus for establishing a negative body potential in a memory cell

Read retry scratch space

Memory array reset read operation

Apparatus and methods including establishing a negative body potent...

Memory array reset read operation

Apparatus and methods including establishing a negative body potent...

Methods including establishing a negative body potential in a memor...

Determining soft data for combinations of memory cells

Determining soft data for combinations of memory cells

Loading trim address and trim data pairs

Determining soft data for combinations of memory cells

Memory block testing

Memory block testing

Die based trimming

Output data compression scheme for use in testing IC memories

Output data compression scheme for use in testing IC memories

Programmable logic device macrocell having exclusive lines for feed...

Programmable logic device macrocell with an exclusive feedback and...

Programmable logic device macrocell with an exclusive feedback line...

Programmable logic device macrocell with an exclusive feedback and...

Patents Applicationslast 30 patents

READ RETRY SCRATCH SPACE

MEMORY ARRAY RESET READ OPERATION

APPARATUS FOR ESTABLISHING A NEGATIVE BODY POTENTIAL IN A MEMORY CELL

READ RETRY SCRATCH SPAC

MEMORY ARRAY RESET READ OPERATION

APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...

MEMORY ARRAY RESET READ OPERATION

APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...

APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENT...

DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS

DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS

LOADING TRIM ADDRESS AND TRIM DATA PAIRS

DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS

MEMORY BLOCK TESTING

Memory block testing

DIE BASED TRIMMING